Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions
    1.
    发明授权
    Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions 有权
    具有片上可编程逻辑的显示处理器集成电路,用于实现定制增强功能

    公开(公告)号:US07782398B2

    公开(公告)日:2010-08-24

    申请号:US10235628

    申请日:2002-09-04

    Abstract: A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing the custom video/image enhancement function.

    Abstract translation: 显示处理器集成电路(例如,用于电视机或数字照相机)包括显示处理器部分和片上可编程逻辑部分。 可以配置或编程片上可编程逻辑部分以实现定制的视频和/或图像增强功能。 因此,通过使可编程逻辑部分被适当地配置或编程,个人电视或照相机制造商可以将他/她自己的定制增强功能结合到显示处理器集成电路中。 在一个实施例中,可编程逻辑部分的编程涉及仅改变一个掩码,从而降低与实现定制视频/图像增强功能相关联的成本,复杂性和时间。

    ASIC having dense mask-programmable portion and related system development method
    2.
    发明授权
    ASIC having dense mask-programmable portion and related system development method 失效
    ASIC具有密集的可编程部分和相关的系统开发方法

    公开(公告)号:US07346876B2

    公开(公告)日:2008-03-18

    申请号:US10944323

    申请日:2004-09-17

    Abstract: A method is disclosed whereby an inexpensive integrated circuit is provided for use in high volume electronic consumer devices of different makes, wherein each different make must perform a different special function. A common function required in all the different makes is realized in a substantially non-customizable portion. A dense mask-programmable portion is provided for realizing a special function. Interface circuitry is provided that enables an external FPGA to perform the special function at system operating speeds during system development. After system development, the circuitry implemented in the external FPGA is technology-mapped to the mask-programmable portion. A single mask is fashioned such that versions of the integrated circuit are produced with their mask-programmable portions customized to perform the special function. I/O terminals that were used to couple to the external FPGA during system development are usable during normal operation to provide system board access to circuitry within the mask-programmable portion.

    Abstract translation: 公开了一种方法,其中提供了用于不同制造的大容量电子消费装置的便宜的集成电路,其中每个不同的制品必须执行不同的特殊功能。 在所有不同的构成中所需的共同功能在基本不可定制的部分中实现。 提供密集的可编程部分,用于实现特殊功能。 提供了接口电路,使得外部FPGA能够在系统开发过程中以系统运行速度执行特殊功能。 系统开发后,外部FPGA中实现的电路技术映射到掩模可编程部分。 形成单个掩模,使得集成电路的版本通过其定制的掩模可编程部分产生以执行特殊功能。 用于在系统开发过程中耦合到外部FPGA的I / O端子在正常操作期间可用,以提供系统板访问掩模可编程部分内的电路。

    Segment buffer loading in a deinterlacer
    3.
    发明授权
    Segment buffer loading in a deinterlacer 有权
    去隔行扫描器中的段缓冲区加载

    公开(公告)号:US07136108B2

    公开(公告)日:2006-11-14

    申请号:US10722323

    申请日:2003-11-25

    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

    Abstract translation: 显示处理器集成电路包括显示处理器部分和片上可编程逻辑部分。 可编程逻辑部分可被配置为实现定制的视频和/或图像增强功能。 显示处理器部分执行基于块的运动检测。 如果对于给定的像素块没有检测到运动,则使用时间插值来填充块中的行间隙。 如果检测到运动,则使用空间插值填充行间隙。 为了保持精度而不会不适当地增加计算复杂度,在不检测到低角度倾斜条件的情况下采用较不复杂的高角度空间插值方法。 因此,在低角度倾斜条件下可以采用更计算密集的低角度空间插值方法。 在读取其他部分的同时进行插值处理的同时,通过采用流水线来编写段缓冲器的部分来减少集成电路成本。

    Segment buffer loading in a deinterlacer
    4.
    发明授权
    Segment buffer loading in a deinterlacer 有权
    去隔行扫描器中的段缓冲区加载

    公开(公告)号:US07349030B2

    公开(公告)日:2008-03-25

    申请号:US11586297

    申请日:2006-10-24

    Abstract: A display processor integrated circuit includes a display processor portion and an on-chip programmable logic portion. The programmable logic portion can be configured to implement custom video and/or image enhancement functions. The display processor portion performs block-based motion detection. If no motion is detected for a given block of pixels, then interline gaps in the block are filled using temporal interpolation. If motion is detected, then interline gaps are filled using spatial interpolation. To maintain accuracy without unduly increasing computational complexity, a less complex high angle spatial interpolation method is employed where a low angle tilt condition is not detected. A more computationally intensive low angle spatial interpolation method can therefore be employed in low angle tilt conditions. Integrated circuit cost is reduced by employing pipelining to write parts of segment buffers at the same time that other parts are being read to perform the interpolation process.

    Abstract translation: 显示处理器集成电路包括显示处理器部分和片上可编程逻辑部分。 可编程逻辑部分可被配置为实现定制的视频和/或图像增强功能。 显示处理器部分执行基于块的运动检测。 如果对于给定的像素块没有检测到运动,则使用时间插值来填充块中的行间隙。 如果检测到运动,则使用空间插值填充行间隙。 为了保持精度而不会不适当地增加计算复杂度,在不检测到低角度倾斜条件的情况下采用较不复杂的高角度空间插值方法。 因此,在低角度倾斜条件下可以采用更计算密集的低角度空间插值方法。 在读取其他部分的同时进行插值处理的同时,通过采用流水线来编写段缓冲器的部分来减少集成电路成本。

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