公开(公告)号：US09564406B1

公开(公告)日：2017-02-07

申请号：US14814316

申请日：2015-07-30

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Yan Xun Xue ,  Man Sheng Hu ,  Jun Lu ,  Yueh-Se Ho ,  Hamza Yilmaz

IPC分类号： H01L23/495 ,  H01L23/62 ,  H01L23/29 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L21/304 ,  H01L21/78 ,  H01L21/56 ,  H01L21/311 ,  H01L25/00 ,  H01L23/544

CPC分类号： H01L25/0652 ,  H01L21/304 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/4825 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/62 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2223/54486 ,  H01L2224/03318 ,  H01L2224/03334 ,  H01L2224/03602 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/0615 ,  H01L2224/11318 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/18161 ,  H01L2924/301 ,  H02J7/0029 ,  H02J2007/0039 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

摘要： The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

摘要翻译： 本发明公开了小尺寸电池保护封装，并提供了制造小尺寸电池保护封装的工艺。 电池保护封装包括第一共漏极金属氧化物半导体场效应晶体管（MOSFET），第二共漏极MOSFET，功率控制集成电路（IC），多个焊球，多个导电凸块和 包装层 功率控制IC垂直堆叠在第一和第二共漏极MOSFET的顶部。 功率控制IC的至少大部分部分和多个焊球的至少大部分被嵌入到包装层中。 制造电池保护封装的过程包括制造功率控制IC的步骤; 制造公共漏极MOSFET晶圆; 将功率控制IC与公共漏极MOSFET晶片和连接引脚排列集成; 形成包装层; 应用研磨工艺; 形成金属层; 并分离电池保护包。

公开(公告)号：US20160035653A1

公开(公告)日：2016-02-04

申请号：US14447956

申请日：2014-07-31

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Jun Lu ,  Hamza Yilmaz ,  Hongtao Gao

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/78

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/03436 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/2929 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： The present invention discloses the MCSP power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer. Thus, individual MCSP power semiconductor devices are separated by cutting the wafer, the conductive adhesive, the metal foil layer and the composite tape along the scribe lines between adjacent semiconductor chips formed on the front of the wafer.

摘要翻译： 本发明公开了MCSP功率半导体器件及其制备方法。 在本发明的方法中，使用导电性粘合剂层将金属箔层附着在晶片的背面，复合带层压在金属箔层上。 因此，通过沿形成在晶片前面的相邻半导体芯片之间的切割线切割晶片，导电粘合剂，金属箔层和复合带来分离各个MCSP功率半导体器件。

公开(公告)号：US20140315350A1

公开(公告)日：2014-10-23

申请号：US14317152

申请日：2014-06-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Zhiqiang Niu ,  Guo Feng Lian ,  Hong Xia Fu ,  Yu Ping Gong

IPC分类号： H01L21/461 ,  H01L23/00 ,  H01L21/71

CPC分类号： H01L24/11 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/492 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.

摘要翻译： 用于MCSP的晶片工艺包括：在芯片的焊盘上沉积金属凸块; 在晶片的边缘处形成未覆盖的环以暴露位于两个相邻芯片之间的每个划线的端部，在晶片的前表面上形成覆盖金属凸块的第一封装层; 稀释第一包装层以暴露金属凸块; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 按顺序在凹陷空间中在晶片的底面沉积金属种子层和厚金属层; 切断晶片的边缘部分; 以及通过切割穿过第一包装层，晶片以及沿着划线的金属种子和金属层将单独的芯片与晶片分离。

公开(公告)号：US09685430B2

公开(公告)日：2017-06-20

申请号：US14965787

申请日：2015-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Hua Pan ,  Ming-Chen Lu ,  Yueh-Se Ho ,  Jun Lu

IPC分类号： H01L25/00 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/528 ,  H01L25/16 ,  H01L23/538

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/165 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/73204 ,  H01L2224/73223 ,  H01L2224/73255 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92125 ,  H01L2224/92226 ,  H01L2224/92244 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/014

摘要： A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.

公开(公告)号：US09136154B2

公开(公告)日：2015-09-15

申请号：US14533366

申请日：2014-11-05

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.

摘要翻译： 可以由垂直导电功率半导体器件晶片制造无基底复合功率半导体器件，该晶片包括通过以下步骤：在顶部金属层的顶部上形成焊料凸块;顶部金属层位于晶片的顶表面上; b）在焊料凸块周围形成晶片级模制，使得焊料凸块通过晶片级模制件的顶部暴露; c）研磨器件晶片的背面以将器件晶片的半导体材料部分的总厚度减小到最终厚度; 以及d）在所述晶片的后表面上形成背金属。

公开(公告)号：US09837386B2

公开(公告)日：2017-12-05

申请号：US14993971

申请日：2016-01-12

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Xiaotian Zhang ,  Shekar Mallikarjunaswamy ,  Zhiqiang Niu ,  Cheow Khoon Oh ,  Yueh-Se Ho

IPC分类号： H01L25/07 ,  H01L23/49 ,  H02M3/158 ,  H01L29/78 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/37 ,  H01L24/40 ,  H01L24/73 ,  H01L25/16 ,  H01L29/7827 ,  H01L2224/16225 ,  H01L2224/376 ,  H01L2224/4005 ,  H01L2224/40137 ,  H01L2224/73255 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14252 ,  H02M3/158 ,  H01L2224/37599

摘要： A power conversion device including a low-side MOSFET, a high-side MOSFET and an integrated control IC chip is disclosed. The power conversion device further includes a substrate comprising a first mounting area having a first group of welding discs and a second mounting area having a second group of welding discs; a first chip flipped and attached to the first mounting area; a second chip flipped and attached to the second mounting area; a metal clip; and a molding body covering a front surface of the substrate, the first chip, the second chip and the metal clip. Metal pads on a front side of the first chip is attached to the first group of welding discs. Metal pads on a front side of the second chip is attached to the second group of welding discs. The metal clip connects a connection pad to a back metal layer of the first chip.

公开(公告)号：US09768146B2

公开(公告)日：2017-09-19

申请号：US15387630

申请日：2016-12-21

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Yan Xun Xue ,  Man Sheng Hu ,  Jun Lu ,  Yueh-Se Ho ,  Hamza Yilmaz

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/304 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/544 ,  H01L21/66 ,  H01L21/48 ,  H01L23/495 ,  H02J7/00

CPC分类号： H01L25/0652 ,  H01L21/304 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/4825 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/62 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2223/54486 ,  H01L2224/03318 ,  H01L2224/03334 ,  H01L2224/03602 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/0615 ,  H01L2224/11318 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/18161 ,  H01L2924/301 ,  H02J7/0029 ,  H02J2007/0039 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

摘要： The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

公开(公告)号：US20170033060A1

公开(公告)日：2017-02-02

申请号：US14814316

申请日：2015-07-30

申请人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED

发明人： Zhiqiang Niu ,  Yan Xun Xue ,  Man Sheng Hu ,  Jun Lu ,  Yueh-Se Ho ,  Hamza Yilmaz

IPC分类号： H01L23/62 ,  H01L21/66 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683 ,  H01L23/495 ,  H01L21/304 ,  H01L21/78 ,  H01L21/56 ,  H01L21/311 ,  H01L25/00 ,  H01L23/544 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L21/304 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/4825 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/78 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/62 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/89 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2223/54486 ,  H01L2224/03318 ,  H01L2224/03334 ,  H01L2224/03602 ,  H01L2224/03849 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/0615 ,  H01L2224/11318 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/18161 ,  H01L2924/301 ,  H02J7/0029 ,  H02J2007/0039 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

摘要： The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer. The process of fabricating battery protection packages includes steps of fabricating power control ICs; fabricating common-drain MOSFET wafer; integrating the power control ICs with the common-drain MOSFET wafer and connecting pinouts; forming a packaging layer; applying grinding processes; forming a metal layer; and singulating battery protection packages.

摘要翻译： 本发明公开了小尺寸电池保护封装，并提供了制造小尺寸电池保护封装的工艺。 电池保护封装包括第一共漏极金属氧化物半导体场效应晶体管（MOSFET），第二共漏极MOSFET，功率控制集成电路（IC），多个焊球，多个导电凸块和 包装层 功率控制IC垂直堆叠在第一和第二共漏极MOSFET的顶部。 功率控制IC的至少大部分部分和多个焊球的至少大部分被嵌入到包装层中。 制造电池保护封装的过程包括制造功率控制IC的步骤; 制造公共漏极MOSFET晶圆; 将功率控制IC与公共漏极MOSFET晶片和连接引脚排列集成; 形成包装层; 应用研磨工艺; 形成金属层; 并分离电池保护包。

公开(公告)号：US09318424B2

公开(公告)日：2016-04-19

申请号：US14447956

申请日：2014-07-31

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Jun Lu ,  Hamza Yilmaz ,  Hongtao Gao

IPC分类号： H01L23/495 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L23/49562 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/94 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/03436 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/2929 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

摘要： The present invention discloses the MCSP power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer. Thus, individual MCSP power semiconductor devices are separated by cutting the wafer, the conductive adhesive, the metal foil layer and the composite tape along the scribe lines between adjacent semiconductor chips formed on the front of the wafer.

摘要翻译： 本发明公开了MCSP功率半导体器件及其制备方法。 在本发明的方法中，使用导电性粘合剂层将金属箔层附着在晶片的背面，复合带层压在金属箔层上。 因此，通过沿形成在晶片前面的相邻半导体芯片之间的切割线切割晶片，导电粘合剂，金属箔层和复合带来分离各个MCSP功率半导体器件。

公开(公告)号：US20160099238A1

公开(公告)日：2016-04-07

申请号：US14965787

申请日：2015-12-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhiqiang Niu ,  Hua Pan ,  Ming-Chen Lu ,  Yueh-Se Ho ,  Jun Lu

IPC分类号： H01L25/00 ,  H01L23/495 ,  H01L21/768 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L25/165 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16245 ,  H01L2224/16258 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/73204 ,  H01L2224/73223 ,  H01L2224/73255 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92125 ,  H01L2224/92226 ,  H01L2224/92244 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/014

摘要： The present invention discloses anew embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, no that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.

摘要翻译： 本发明公开了一种新的嵌入式封装，其包括：预成型引线框架，其上附着有多个芯片，其中模制材料填充引线框架的空隙，而不是引线框架完全固定; 布置在引线框周围的多个引脚; 附接在芯片上并将芯片电连接在一起的金属夹子; 覆盖芯片的第一层叠层，引线框架，金属夹和销; 导电插头和延伸部，其形成为将芯片的电极连接到相应的引脚或将芯片连接在一起。 具有三维堆叠能力的本发明的新嵌入式封装提高了厚度，热和电性能以及灵活的功率和逻辑混合设计。