公开(公告)号：US08846532B2

公开(公告)日：2014-09-30

申请号：US13621289

申请日：2012-09-16

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Ming Sun

IPC分类号： H01L21/302

CPC分类号： B32B38/0012 ,  B32B2038/0016 ,  B32B2038/0092 ,  B32B2309/10 ,  B32B2457/14 ,  H01L21/67132 ,  H01L21/6836 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/0556 ,  H01L2224/05568 ,  H01L2224/06183 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17104 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552

摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

摘要翻译： 公开了一种用于超薄晶片背面处理的方法和装置。 该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。 超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。 晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。 还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

公开(公告)号：US20150340301A1

公开(公告)日：2015-11-26

申请号：US14818128

申请日：2015-08-04

申请人： ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L27/088 ,  H01L23/00 ,  H01L29/78

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A vertical conductive power semiconductor device may include a substrate with a top metal layer located on a top surface of the substrate, solder bumps deposited on top of the top metal layer, and wafer level molding surrounding the solder bumps and leaving the solder bumps at least partly exposed.

摘要翻译： 垂直导电功率半导体器件可以包括具有位于衬底的顶表面上的顶部金属层的衬底，沉积在顶部金属层顶部上的焊料凸起以及围绕焊料凸块的晶片级成型以及至少留下焊料凸块 部分暴露。

公开(公告)号：US09136154B2

公开(公告)日：2015-09-15

申请号：US14533366

申请日：2014-11-05

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L21/56 ,  H01L23/495 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.

摘要翻译： 可以由垂直导电功率半导体器件晶片制造无基底复合功率半导体器件，该晶片包括通过以下步骤：在顶部金属层的顶部上形成焊料凸块;顶部金属层位于晶片的顶表面上; b）在焊料凸块周围形成晶片级模制，使得焊料凸块通过晶片级模制件的顶部暴露; c）研磨器件晶片的背面以将器件晶片的半导体材料部分的总厚度减小到最终厚度; 以及d）在所述晶片的后表面上形成背金属。

公开(公告)号：US20130273697A1

公开(公告)日：2013-10-17

申请号：US13914383

申请日：2013-06-10

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Zhi Qiang Niu ,  Jun Lu ,  Tao Feng

IPC分类号： H01L21/48

CPC分类号： H01L21/4871 ,  H01L21/4821 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/39 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication.

摘要翻译： 本发明公开了一种用于功率半导体器件的混合合金引线框架，其包括多个散热器和引脚阵列; 散热器由第一材料制成，其上部具有定位孔，在其下部中心处具有焊接区，而销阵列由与第一材料不同的第二材料制成，具有多个 的端子分别从其上端和下端引出。 散热器定位在引线框组件焊接板上，引脚定位在引线框组件焊接板上的上散热器和下散热器之间的区域中。 本发明的功率半导体装置用混合合金引线框架，改善了引线框架的散热，降低了引线框架的制造成本，提高了制造的灵活性。

公开(公告)号：US09355953B2

公开(公告)日：2016-05-31

申请号：US14518845

申请日：2014-10-20

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Anup Bhalla

IPC分类号： H01L29/66 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC分类号： H01L23/49844 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.

摘要翻译： 公开了一种具有基板侧暴露的器件侧电极（SEDE）的半导体器件。 半导体器件在器件侧具有器件侧，衬底侧和半导体器件区（SDR）的半导体衬底（SCS）。 形成器件侧电极（DSE）用于器件操作。 通过衬底沟槽（TST）延伸通过SCS，达到DSE将其变成SEDE。 SEDE可以通过TST通过导电互连器相互连接。 可以包括在SSE上面的衬底侧电极（SSE）和窗口化的衬底侧钝化（SSPV）。 SSPV定义了在设备封装期间扩展焊料材料的SSE区域。 可以包括下面覆盖SEDE的器件侧的器件侧钝化（DSPV）。 DSE还可以包括在SEDE下面堆叠的扩展支撑凸缘，用于在晶片间加工包装期间对其进行结构支持。 延伸支撑突出到主SCS平面上的预计占地面积基本上可以包围SEDE相应的预计占地面积。

公开(公告)号：US20150056752A1

公开(公告)日：2015-02-26

申请号：US14533366

申请日：2014-11-05

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Zhiqiang Niu ,  Yuping Gong ,  Ruisheng Wu ,  Ping Huang ,  Lei Shi ,  Yueh-Se Ho

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78

CPC分类号： H01L21/6836 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76897 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/495 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/40 ,  H01L24/73 ,  H01L24/94 ,  H01L25/50 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/051 ,  H01L2224/05139 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/06181 ,  H01L2224/1184 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/37099

摘要： A substrate-less composite power semiconductor device may be fabricated from a vertical conductive power semiconductor device wafer that includes a top metal layer located on a top surface of the wafer by a) forming solder bumps on top of the top metal layer; b) forming wafer level molding around the solder bumps such that the solder bumps are exposed through a top of the wafer level molding; c) grinding a back side of the device wafer to reduce a total thickness of a semiconductor material portion of the device wafer to a final thickness; and d) forming a back metal on a back surface of the wafer.

摘要翻译： 可以由垂直导电功率半导体器件晶片制造无基底复合功率半导体器件，该晶片包括通过以下步骤：在顶部金属层的顶部上形成焊料凸块;顶部金属层位于晶片的顶表面上; b）在焊料凸块周围形成晶片级模制，使得焊料凸块通过晶片级模制件的顶部暴露; c）研磨器件晶片的背面以将器件晶片的半导体材料部分的总厚度减小到最终厚度; 以及d）在所述晶片的后表面上形成背金属。

公开(公告)号：US20150035049A1

公开(公告)日：2015-02-05

申请号：US14518845

申请日：2014-10-20

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Tao Feng ,  Anup Bhalla

IPC分类号： H01L23/498

CPC分类号： H01L23/49844 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/781 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.

摘要翻译： 公开了一种具有基板侧暴露的器件侧电极（SEDE）的半导体器件。 半导体器件在器件侧具有器件侧，衬底侧和半导体器件区（SDR）的半导体衬底（SCS）。 形成器件侧电极（DSE）用于器件操作。 通过衬底沟槽（TST）延伸通过SCS，达到DSE将其变成SEDE。 SEDE可以通过TST通过导电互连器相互连接。 可以包括在SSE上面的衬底侧电极（SSE）和窗口化的衬底侧钝化（SSPV）。 SSPV定义了在设备封装期间扩展焊料材料的SSE区域。 可以包括下面覆盖SEDE的器件侧的器件侧钝化（DSPV）。 DSE还可以包括在SEDE下面堆叠的扩展支撑凸缘，用于在晶片间加工包装期间对其进行结构支持。 延伸支撑突出到主SCS平面上的预计占地面积基本上可以包围SEDE相应的预计占地面积。