公开(公告)号：US08564106B2

公开(公告)日：2013-10-22

申请号：US13360044

申请日：2012-01-27

Applicant: Swee Kwang Chua ,  Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo

Inventor： Swee Kwang Chua ,  Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/9202

Abstract: Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

公开(公告)号：US08232657B2

公开(公告)日：2012-07-31

申请号：US12973607

申请日：2010-12-20

Applicant: Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

Inventor： Suan Jeung Boon ,  Meow Koon Eng ,  Yong Poo Chia

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract translation: 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US20100146780A1

公开(公告)日：2010-06-17

申请号：US12705923

申请日：2010-02-15

Applicant: Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

Inventor： Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

IPC: H05K3/02

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/00 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49794 ,  H01L2924/00

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract translation: 描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面 的基底以露出封装级触点的背面。 因此，形成了基本上真正的芯片级封装。 通过用密封剂填充芯片之间的间隙来形成多芯片模块。 在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。 在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

公开(公告)号：US07712211B2

公开(公告)日：2010-05-11

申请号：US10744632

申请日：2003-12-23

Applicant: Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

Inventor： Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

IPC: H05K3/30

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/00 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49794 ,  H01L2924/00

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract translation: 描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面 的基底以露出封装级触点的背面。 因此，形成了基本上真正的芯片级封装。 通过用密封剂填充芯片之间的间隙来形成多芯片模块。 在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。 在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

公开(公告)号：US20100072603A1

公开(公告)日：2010-03-25

申请号：US12627352

申请日：2009-11-30

Applicant: Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

Inventor： Suan Jeung Boon ,  Yong Poo Chia ,  Meow Koon Eng ,  Siu Waf Low

IPC: H01L23/498

CPC classification number: H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L25/105 ,  H01L2225/1058 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

Abstract: A sacrificial substrate for fabricating semiconductor device assemblies and packages with edge contacts includes conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. A semiconductor device assembly or package includes a semiconductor device, a redistribution layer over an active surface of the semiconductor device, and dielectric material coating at least portions of an outer periphery of the semiconductor device. Peripheral sections of contacts are located on the peripheral edge and electrically isolated therefrom by the dielectric coating. The contacts may also include upper sections that extend partially over the active surface of the semiconductor device. The assembly or package may include any type of semiconductor device, including a processor, a memory device, and emitter, or an optically sensitive device.

Abstract translation: 用于制造具有边缘触点的半导体器件组件和封装的牺牲衬底包括其表面上的导电元件，其被定位成沿着设备衬底上的每个相邻的一对半导体器件之间的街道排列。 半导体器件组件或封装包括半导体器件，半导体器件的有源表面上的再分布层，以及涂覆半导体器件外周的至少部分的电介质材料。 触点的周边部分位于外围边缘，并通过电介质涂层与其隔离。 触点还可以包括在半导体器件的有效表面上部分延伸的上部部分。 组件或封装可以包括任何类型的半导体器件，包括处理器，存储器件和发射极，或光敏器件。

公开(公告)号：US07485562B2

公开(公告)日：2009-02-03

申请号：US11028374

申请日：2005-01-03

Applicant: Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

Inventor： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

Abstract translation: 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底的背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。 还公开了包含包装的计算系统。

公开(公告)号：US07274094B2

公开(公告)日：2007-09-25

申请号：US10233319

申请日：2002-08-28

Applicant: Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

Inventor： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

IPC: H01L23/495

CPC classification number: H01L31/0203 ,  H01L2224/16245

Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

Abstract translation: 无引线图像传感器封装及其组装方法。 在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。 透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。 透明盖通过密封剂材料保持在孔的适当位置。 图像传感器芯片的背面被暴露。 在特别适用于高端图像传感器的第二实施例中，不需要密封材料。 相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。 形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

公开(公告)号：US08536702B2

公开(公告)日：2013-09-17

申请号：US13492554

申请日：2012-06-08

Applicant: Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

Inventor： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC: H01L23/48

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US08362594B2

公开(公告)日：2013-01-29

申请号：US13074938

申请日：2011-03-29

Applicant: Swee Kwang Chua ,  Suan Jeung Boon ,  Yong Poo Chia

Inventor： Swee Kwang Chua ,  Suan Jeung Boon ,  Yong Poo Chia

IPC: H01L21/44 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/24227 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/4824 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/4943 ,  H01L2224/76155 ,  H01L2224/78301 ,  H01L2224/78302 ,  H01L2224/85045 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a method of manufacturing a semiconductor device includes forming a plurality of first side trenches to an intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes removing material from a second side of the molded portion at areas aligned with the first side trenches, wherein removing the material forms openings through the molded portion. The method further includes forming a plurality of electrical contacts at the second side of the molded portion at the openings and electrically connecting the second side contacts to corresponding bond-sites on the dies.

Abstract translation: 本文公开了包括用于形成这种互连的互连和方法的半导体器件和组件。 制造半导体器件的方法的一个实施例包括在具有排成行和列的多个管芯的模制晶片的模制部分中形成多个第一侧沟槽至中间深度。 该方法还包括在与第一侧沟槽对准的区域处从模制部分的第二侧移除材料，其中去除材料通过模制部分形成开口。 该方法还包括在开口处在模制部分的第二侧处形成多个电触头，并将第二侧触点电连接到模具上相应的键合位置。

公开(公告)号：US08198720B2

公开(公告)日：2012-06-12

申请号：US12955666

申请日：2010-11-29

Applicant: Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

Inventor： Meow Koon Eng ,  Yong Poo Chia ,  Suan Jeung Boon

IPC: H01L25/065

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 第二管芯封装，其具有附接到第一封装的底侧的顶侧，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。