公开(公告)号：US08629054B2

公开(公告)日：2014-01-14

申请号：US13441533

申请日：2012-04-06

Applicant: Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

Inventor： Boon Suan Jeung ,  Eng Meow Koon ,  Chia Yong Poo

IPC: H01L21/44

CPC classification number: H01L23/5283 ,  H01L21/4853 ,  H01L21/76885 ,  H01L21/82 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/522 ,  H01L24/19 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/82 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/4554 ,  H01L2224/45669 ,  H01L2224/48095 ,  H01L2224/48145 ,  H01L2224/48464 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73267 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85909 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.

Abstract translation: 包括用于形成这种互连结构的互连结构和方法的封装半导体组件在本文中公开。 封装半导体组件的一个实施例包括具有第一结合位置的支撑构件和由具有第二结合位点的支撑构件承载的模具。 互连结构连接在第一和第二结合位点之间，并且包括耦合到第一和第二键合位置中的至少一个的导线。 互连结构还包括在第一和第二键合位点之间耦合到线的第三键位置。

公开(公告)号：US08065792B2

公开(公告)日：2011-11-29

申请号：US12705923

申请日：2010-02-15

Applicant: Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

Inventor： Yong Poo Chia ,  Low Siu Waf ,  Suan Jeung Boon ,  Eng Meow Koon ,  Swee Kwang Chua

IPC: H05K3/20

CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L22/00 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T29/49794 ,  H01L2924/00

Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.

Abstract translation: 描述了一种用于封装集成电路芯片（裸片）的方法，其包括提供具有封装级触点的基底基板，用粘合剂涂覆基底基板，将模具放置在粘合剂上，将模具电连接到封装级触点，以及去除背面 的基底以露出封装级触点的背面。 因此，形成了基本上真正的芯片级封装。 通过用密封剂填充芯片之间的间隙来形成多芯片模块。 在一个实施例中，芯片通过基底衬底中的封装级触点之间的电连接互连。 在一个实施例中，每个具有芯片的基板通过形成在对准的锯道中的通孔背靠背粘合以互连背对背芯片组件。

公开(公告)号：US07947529B2

公开(公告)日：2011-05-24

申请号：US11923290

申请日：2007-10-24

Applicant: Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

Inventor： Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US20100140794A1

公开(公告)日：2010-06-10

申请号：US12705277

申请日：2010-02-12

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

IPC: H01L23/498

CPC classification number: H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 一种装置包括集成电路管芯，其包括具有顶层，底层和在顶层和底层之间延伸的周边边缘表面的主体。 集成电路管芯还包括主体上的接合焊盘，外围边缘表面处的边缘接触以及将接合焊盘连接到边缘接触件的线。 边缘接触包括底面，其基本上在与包封模具的密封剂的表面相同的平面内。 公开了附加装置，系统和方法。

公开(公告)号：US20090045489A1

公开(公告)日：2009-02-19

申请号：US11923290

申请日：2007-10-24

Applicant: Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

Inventor： Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung ,  Tay Wuu Yean

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/58

CPC classification number: H01L23/49527 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2924/01078

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，一种制造微电子器件的方法包括将具有第一介电壳体的第一管芯封装堆叠在具有第二介电壳体的第二管芯封装的顶部上，使第一壳体的侧表面上的第一金属引线与第二金属 在第二壳体的第二侧表面处引导，并且形成将单独的第一引线连接到单独的第二引线的金属焊料连接器。 在另一个实施例中，制造微电子器件的方法还可以包括通过将金属焊料施加到第一侧表面的一部分，第二侧表面的一部分，以及跨越第一管芯封装和第二侧表面之间的间隙来形成连接器 第二管芯封装，使得连接器由金属焊料形成，其润湿到各个第一引线和各个第二引线。

公开(公告)号：US20090026600A1

公开(公告)日：2009-01-29

申请号：US11863425

申请日：2007-09-28

Applicant: Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

Inventor： Eng Meow Koon ,  Chia Yong Poo ,  Boon Suan Jeung

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L25/105 ,  H01L21/50 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49555 ,  H01L23/49811 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/17 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract translation: 本文公开了微电子管芯封装，管芯封装的堆叠系统及其制造方法。 在一个实施例中，堆叠封装的系统包括具有底侧的第一裸片封装，第一电介质外壳和第一金属引线; 具有附接到第一封装的底侧的顶侧的第二管芯封装，具有侧面的电介质外壳和与第一金属引线对准并朝向第一金属引线突出的第二金属引线，并且包括外表面和内表面区域， 一般面向外侧; 和金属焊接连接器将各个第一引线连接到单独的第二引线。 在另一个实施例中，各个第二引线具有“L”形状并且物理地接触相应的单个第一引线。 在另一个实施例中，各个第二引线具有“C”形并且包括向第二壳体的侧面突出的分层部分。

公开(公告)号：US06836009B2

公开(公告)日：2004-12-28

申请号：US10230761

申请日：2002-08-28

Applicant: Eng Meow Koon ,  Low Siu Waf ,  Chan Min Yu ,  Chia Yong Poo ,  Ser Bok Leng ,  Zhou Wei

Inventor： Eng Meow Koon ,  Low Siu Waf ,  Chan Min Yu ,  Chia Yong Poo ,  Ser Bok Leng ,  Zhou Wei

IPC: H01L2941

CPC classification number: H01L21/4842 ,  H01L22/10 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract translation: 微电子部件封装包括耦合到微电子部件并且具有向外延伸超过密封剂的外围边缘的暴露长度的多个电引线。 多个端子可以位于密封剂的端面附近，并且这些端子可以电耦合到相同的引线。 这可以有助于使用引线作为常规引线封装将微电子部件连接到基板。 然而，这些端子可以促进引线封装与一个或多个额外的微电子部件例如BGA封装的堆叠。

公开(公告)号：US08637973B2

公开(公告)日：2014-01-28

申请号：US11692068

申请日：2007-03-27

Applicant: Eng Meow Koon ,  Low Siu Waf ,  Chan Min Yu ,  Chia Yong Poo ,  Ser Bok Leng ,  Zhou Wei

Inventor： Eng Meow Koon ,  Low Siu Waf ,  Chan Min Yu ,  Chia Yong Poo ,  Ser Bok Leng ,  Zhou Wei

IPC: H01L23/52

CPC classification number: H01L21/4842 ,  H01L22/10 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Abstract translation: 微电子部件封装包括耦合到微电子部件并且具有向外延伸超过密封剂的外围边缘的暴露长度的多个电引线。 多个端子可以位于密封剂的端面附近，并且这些端子可以电耦合到相同的引线。 这可以有助于使用引线作为常规引线封装将微电子部件连接到基板。 然而，这些端子可以促进引线封装与一个或多个额外的微电子部件例如BGA封装的堆叠。

公开(公告)号：US08115306B2

公开(公告)日：2012-02-14

申请号：US12705277

申请日：2010-02-12

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

IPC: H01L23/48

CPC classification number: H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 一种装置包括集成电路管芯，其包括具有顶层，底层和在顶层和底层之间延伸的周边边缘表面的主体。 集成电路管芯还包括主体上的接合焊盘，外围边缘表面处的边缘接触以及将接合焊盘连接到边缘接触件的线。 边缘接触包括底面，其基本上在与包封模具的密封剂的表面相同的平面内。 公开了附加装置，系统和方法。

公开(公告)号：US20100068851A1

公开(公告)日：2010-03-18

申请号：US12624774

申请日：2009-11-24

Applicant: Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

Inventor： Boon Suan Jeung ,  Chia Yong Poo ,  Low Siu Waf ,  Eng Meow Koon ,  Chua Swee Kwang ,  Huang Shuang Wu ,  Neo Yong Loo ,  Zhou Wei

IPC: H01L21/50

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Abstract translation: 提供了用于封装晶圆级封装中集成电路芯片的系统和方法。 芯片的有源电路区域耦合到城堡块，并且根据实施例，输入/输出焊盘。 城堡块和输入/输出垫通过密封剂封装并保持就位。 当制造设备时，将城堡块和输入/输出垫片穿过。 如果需要，可以使其上制造器件的晶片部分变薄。 封装可以用作无引线芯片载体封装，或者可以堆叠在彼此之上。 当堆叠时，封装的相应触点优选地联接。 当芯片被激活时，可以将数据写入和从芯片接收。 可以通过将适当的信号或信号施加到适当的触点或触点来激活芯片。