REFERENCE CURRENT GENERATION CIRCUIT
    4.
    发明公开

    公开(公告)号:US20240176380A1

    公开(公告)日:2024-05-30

    申请号:US18166265

    申请日:2023-02-08

    发明人: HIROYUKI KIMURA

    IPC分类号: G05F3/26 G05F1/56

    CPC分类号: G05F3/262 G05F1/561

    摘要: The disclosure includes: a third current mirror, through which a current obtained by adding a first reference current copied by a first current mirror and a second reference current copied by a second current mirror is made to flow; a reference resistor of the first type, through which the first reference current obtained by subtracting the second reference current copied by the first current mirror from one output of the third current mirror is made to flow; and a reference resistor of the second type, through which the second reference current obtained by subtracting the first reference current copied by the first current mirror from the other output of the third current mirror is made to flow. By the third current mirror, voltage drops at the reference resistor of the first type and the reference resistor of the second type are made the same, and the second reference current is set to be inversely proportional to the resistance value of the reference resistor of the second type.

    OUTPUT DETECTION CIRCUIT
    6.
    发明公开

    公开(公告)号:US20240201724A1

    公开(公告)日:2024-06-20

    申请号:US18155490

    申请日:2023-01-17

    发明人: HIROYUKI KIMURA

    IPC分类号: G05F3/26 G05F1/46

    CPC分类号: G05F3/262 G05F1/461

    摘要: The disclosure: a positive mirror FET, through which a positive mirror current that is proportional to a positive-direction current in currents of an output FET in positive and negative directions is made to flow; a first operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the positive mirror current of the positive mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the positive mirror current of the positive mirror FET by converting an output voltage into a current and feeding back the current to the other end; a negative mirror FET, through which a negative mirror current that is proportional to a negative-direction current in the currents of the output FET in positive and negative directions is made to flow; and a second operational amplifier, receiving a constant voltage at one end, receiving an upstream side voltage regarding the negative mirror current of the negative mirror FET at the other end, and outputting a voltage corresponding to the upstream side voltage regarding the negative mirror current of the negative mirror FET by converting an output voltage into a current and feeding back the current to the other end. A detection value is output based on an output current obtained by adding a positive output current corresponding to the output of the first operational amplifier and a negative output current corresponding to the output of the second operational amplifier.

    SWITCH CIRCUIT
    7.
    发明公开
    SWITCH CIRCUIT 审中-公开

    公开(公告)号:US20230396148A1

    公开(公告)日:2023-12-07

    申请号:US17858304

    申请日:2022-07-06

    发明人: Hiroyuki KIMURA

    IPC分类号: H02M1/08 H02M1/00 H02M3/155

    摘要: A switch circuit includes: a p-channel pass transistor, in which the source is connected to a power source and the drain is connected to a load; and a gate drive circuit, which is connected to the gate of the pass transistor. The gate drive circuit includes: a first transistor, through which a first current is made to flow by turn-on of an on/off signal; and an amplifier, in which a reference voltage corresponding to the first current is input to the negative input end, and a gate voltage of the gate is input to the positive input end, and which controls a gate current from the gate by an output from the output end in a manner that the gate voltage matches the reference voltage, and is capable of setting a maximum current of the output. A soft-on time from turn-on of the on/off signal to turn-on of the pass transistor is set by setting the maximum current according to the gate capacitance of the pass transistor.

    Clock generation circuit
    8.
    发明授权

    公开(公告)号:US11669125B1

    公开(公告)日:2023-06-06

    申请号:US17833995

    申请日:2022-06-07

    发明人: Hiroyuki Kimura

    摘要: The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the output of the second inverter becomes the L level and the clock signal becomes the L level.

    SEMICONDUCTOR DEVICE
    10.
    发明公开

    公开(公告)号:US20240347584A1

    公开(公告)日:2024-10-17

    申请号:US18340485

    申请日:2023-06-23

    摘要: [Problem to be solved] To reduce recovery loss.
    [Solution] A semiconductor device 10 includes: an anode electrode 20, formed on a front surface of a semiconductor substrate 12; a cathode electrode 22, formed on a back surface; a P layer 16, formed on the anode electrode 20 side; an N layer 14, formed on the cathode electrode 22 side; an N+ layer 26, arranged between the P layer 16 and the N layer 14 and having a higher carrier concentration than the N layer 14; and an anode trench 30, which extends from the front surface of the semiconductor substrate 12 toward the back surface side thereof and extends to the N+ layer 26 through the P layer 16, and in which an insulating film 32 is formed between the peripheral N+ layer 26, and a conductive material 34 arranged inside is connected to the anode electrode 20.