公开(公告)号：US08570409B2

公开(公告)日：2013-10-29

申请号：US12909948

申请日：2010-10-22

申请人： Sang-Jun Choi ,  Yoon-Dong Park ,  Chris Hong ,  Dae-Lok Bae ,  Jung-Chak Ahn ,  Chang-Rok Moon ,  June-Mo Koo ,  Suk-Pil Kim ,  Hoon-Sang Oh

发明人： Sang-Jun Choi ,  Yoon-Dong Park ,  Chris Hong ,  Dae-Lok Bae ,  Jung-Chak Ahn ,  Chang-Rok Moon ,  June-Mo Koo ,  Suk-Pil Kim ,  Hoon-Sang Oh

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H01L27/14641 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： An image sensor includes a first substrate including a driving element, a first insulation layer on the first substrate and on the driving element, a second substrate including a photoelectric conversion element, and a second insulation layer on the second substrate and on the photoelectric conversion element. A surface of the second insulation layer is on an upper surface of the first insulation layer. The image sensor includes a conductive connector penetrating the second insulation layer and a portion of the first insulation layer. Methods of forming image sensors are also disclosed.

摘要翻译： 图像传感器包括：第一基板，包括驱动元件，第一基板上的第一绝缘层和驱动元件;第二基板，包括光电转换元件;以及第二绝缘层，在第二基板上和光电转换元件 。 第二绝缘层的表面位于第一绝缘层的上表面上。 图像传感器包括穿透第二绝缘层和第一绝缘层的一部分的导电连接器。 还公开了形成图像传感器的方法。

公开(公告)号：US08283711B2

公开(公告)日：2012-10-09

申请号：US12149209

申请日：2008-04-29

申请人： Young-gu Jin ,  Yoon-dong Park ,  Won-joo Kim ,  Seung-hoon Lee ,  Suk-pil Kim

发明人： Young-gu Jin ,  Yoon-dong Park ,  Won-joo Kim ,  Seung-hoon Lee ,  Suk-pil Kim

IPC分类号： H01L29/792

CPC分类号： G11C5/02 ,  G11C5/025 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.

摘要翻译： 提供了一种非易失性存储器件，其可以具有堆叠结构并且可以容易地以增加的密度集成，以及制造和使用非易失性存储器件的方法。 非易失性存储器件可以包括至少一对第一电极线。 至少一个第二电极线可以在所述至少一对第一电极线之间。 至少一个数据存储层可以在至少一对第一电极线和至少一个第二电极线之间，并且可以局部地存储电阻变化。

公开(公告)号：US08058701B2

公开(公告)日：2011-11-15

申请号：US12216094

申请日：2008-06-30

申请人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

发明人： Deok-kee Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  I-hun Song ,  Won-joo Kim ,  Young-gu Jin ,  Hyuk-soon Choi ,  Suk-pil Kim

IPC分类号： H01L23/52

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.

摘要翻译： 提供了防泡结构，反熔丝阵列，制造方法和操作方法。 反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。 反熔丝阵列包括排列成阵列的多个反熔丝结构。

公开(公告)号：US08017477B2

公开(公告)日：2011-09-13

申请号：US11704205

申请日：2007-02-09

申请人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park

发明人： Won-joo Kim ,  Suk-pil Kim ,  Yoon-dong Park

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42352 ,  H01L29/66621 ,  H01L29/7881 ,  H01L29/792

摘要： A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.

摘要翻译： 非易失性存储器件包括多个第一控制栅电极，第二控制栅电极，第一存储节点膜和第二存储节点膜。 第一控制栅电极凹入半导体衬底。 每个第二控制栅电极设置在两个相邻的第一控制栅电极之间。 第二控制栅电极设置在第一控制栅电极上的半导体衬底上。 第一存储节点膜设置在半导体衬底和第一控制栅电极之间。 第二存储节点膜设置在半导体衬底和第二控制栅电极之间。 一种制造非易失性存储器件的方法包括形成第一存储节点膜，形成第一控制栅电极，形成第二存储节点膜，以及形成第二控制栅电极。

公开(公告)号：US20110199602A1

公开(公告)日：2011-08-18

申请号：US13029650

申请日：2011-02-17

申请人： Suk Pil KIM ,  Yoon Dong Park ,  Dong Seok Suh ,  Young Gu Jin ,  Seung Hoon Lee

发明人： Suk Pil KIM ,  Yoon Dong Park ,  Dong Seok Suh ,  Young Gu Jin ,  Seung Hoon Lee

IPC分类号： G01C3/08 ,  H01L31/10 ,  H01L31/00

CPC分类号： H01L27/14607 ,  G01B11/22 ,  G01C3/08 ,  G01S7/4863 ,  G01S17/48 ,  H01L27/144 ,  H01L27/14641 ,  H01L31/02327 ,  H01L31/112

摘要： A sensor, including a plurality of photo gate pairs on a semiconductor substrate, each of the photo gate pairs including a first photo gate and a second photo gate, a first shared floating diffusion region in the semiconductor substrate, and a plurality of first transmission transistors on the semiconductor substrate, wherein each of the plurality of first transmission transistors is adapted to transmit charges to the first shared floating diffusion region in response to a first transmission control signal, the charges being generated in the semiconductor substrate under the first photo gate of each of the plurality of photo gate pairs.

摘要翻译： 一种传感器，包括半导体衬底上的多个光栅对，每个光栅对包括第一光栅和第二光栅，半导体衬底中的第一共享浮动扩散区和多个第一透射晶体管 在半导体基板上，其中多个第一透射晶体管中的每一个适于响应于第一透射控制信号将电荷传输到第一共享浮动扩散区域，电荷在每个第一传输控制信号的第一光栅下的半导体衬底中产生 的多个光栅对。

公开(公告)号：US07910967B2

公开(公告)日：2011-03-22

申请号：US11515024

申请日：2006-09-05

申请人： Sang-min Shin ,  Young-soo Park ,  June-mo Koo ,  Byoung-jae Bae ,  I-hun Song ,  Suk-pil Kim

发明人： Sang-min Shin ,  Young-soo Park ,  June-mo Koo ,  Byoung-jae Bae ,  I-hun Song ,  Suk-pil Kim

IPC分类号： H01L21/00 ,  H01L31/112 ,  H01L23/48

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric capacitor having a three-dimensional structure, a nonvolatile memory device having the same, and a method of fabricating the same are provided. The ferroelectric capacitor may include a trench-type lower electrode, at least one layer formed around the lower electrode, a ferroelectric layer (PZT layer) formed on the lower electrode and the at least one layer and an upper electrode formed on the ferroelectric layer. The at least one layer may be at least one insulating interlayer and the at least one layer may also be at least one diffusion barrier layer. The at least one layer may be formed of an insulating material excluding SiO2 or may have a perovskite crystal structure excluding Pb.

摘要翻译： 提供具有三维结构的铁电电容器，具有其的非易失性存储器件及其制造方法。 铁电电容器可以包括沟槽型下电极，形成在下电极周围的至少一层，形成在下电极和至少一层上的铁电层（PZT层）和形成在铁电层上的上电极。 所述至少一个层可以是至少一个绝缘夹层，并且所述至少一个层也可以是至少一个扩散阻挡层。 所述至少一层可以由除了SiO2之外的绝缘材料形成，或者可以具有不包括Pb的钙钛矿晶体结构。

公开(公告)号：US07910909B2

公开(公告)日：2011-03-22

申请号：US12232745

申请日：2008-09-23

申请人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.

摘要翻译： 提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 提供至少一个第一电极和至少一个第二电极。 所述至少一个第二电极可以穿过所述至少一个第一电极。 至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。 所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

公开(公告)号：US07833890B2

公开(公告)日：2010-11-16

申请号：US12457366

申请日：2009-06-09

申请人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

发明人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07729164B2

公开(公告)日：2010-06-01

申请号：US12010943

申请日：2008-01-31

申请人： Suk-pil Kim ,  Yoon-dong Park ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee

发明人： Suk-pil Kim ,  Yoon-dong Park ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833

摘要： A non-volatile memory device may include at least one semiconductor layer, a plurality of control gate electrodes, a plurality of charge storage layers, at least one first auxiliary electrode, and/or at least one second auxiliary electrode. The plurality of control gate electrodes may be recessed into the semiconductor layer. The plurality of charge storage layers may be between the plurality of control gate electrodes and the semiconductor layer. The first and second auxiliary electrodes may be arranged to face each other. The plurality of control gate electrodes may be between the first and second auxiliary electrodes and capacitively coupled with the semiconductor layer.

摘要翻译： 非易失性存储器件可以包括至少一个半导体层，多个控制栅电极，多个电荷存储层，至少一个第一辅助电极和/或至少一个第二辅助电极。 多个控制栅电极可以凹入半导体层。 多个电荷存储层可以在多个控制栅电极和半导体层之间。 第一和第二辅助电极可以被布置成彼此面对。 多个控制栅电极可以在第一和第二辅助电极之间并与半导体层电容耦合。

公开(公告)号：US07663166B2

公开(公告)日：2010-02-16

申请号：US11723074

申请日：2007-03-16

申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

IPC分类号： H01L27/088

CPC分类号： H01L29/0657 ,  H01L29/42392 ,  H01L29/78696

摘要： Provided are relatively higher-performance wire-type semiconductor devices and relatively economical methods of fabricating the same. A wire-type semiconductor device may include at least one pair of support pillars protruding above a semiconductor substrate, at least one fin protruding above the semiconductor substrate and having ends connected to the at least one pair of support pillars, at least one semiconductor wire having ends connected to the at least one pair of support pillars and being separated from the at least one fin, a common gate electrode surrounding the surface of the at least one semiconductor wire, and a gate insulating layer between the at least one semiconductor wire and the common gate electrode.

摘要翻译： 提供了相对较高性能的线型半导体器件和相对经济的制造方法。 线型半导体器件可以包括突出在半导体衬底上方的至少一对支撑柱，至少一个突出于半导体衬底之上并具有连接到至少一对支撑柱的端子的鳍片，至少一个半导体线材具有 连接到所述至少一对支撑柱并且与所述至少一个鳍分离的端部，围绕所述至少一个半导体线的表面的公共栅电极以及所述至少一个半导体线和所述至少一个半导体线之间的栅极绝缘层 共栅电极。