公开(公告)号：US08873901B2

公开(公告)日：2014-10-28

申请号：US13494445

申请日：2012-06-12

Applicant: Pil-Kyu Kang ,  Dae-Lok Bae ,  Byung-Lyul Park ,  Gil-Heyun Choi

Inventor： Pil-Kyu Kang ,  Dae-Lok Bae ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/124 ,  G02B6/42

CPC classification number: G02B6/305 ,  G02B6/124 ,  G02B6/30 ,  G02B6/4204 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12147

Abstract: Optical input/output (I/O) devices, which include a substrate including a trench, a waveguide within the trench of the substrate; and a photodetector within the trench and optically connected to the waveguide. An upper surface of the photodetector is at a same level as an upper surface of the waveguide.

Abstract translation: 光输入/输出（I / O）器件，其包括衬底，其包括沟槽，衬底的沟槽内的波导; 以及在沟槽内的光电检测器，并且光学连接到波导。 光检测器的上表面与波导的上表面处于同一水平。

公开(公告)号：US08791405B2

公开(公告)日：2014-07-29

申请号：US12911415

申请日：2010-10-25

Applicant: Ho-chul Ji ,  Ki-nam Kim ,  Yong-woo Hyung ,  Kyoung-won Na ,  Kyoung-ho Ha ,  Yoon-dong Park ,  Dae-lok Bae ,  Jin-kwon Bok ,  Pil-kyu Kang ,  Sung-dong Suh ,  Seong-gu Kim ,  Dong-jae Shin ,  In-sung Joe

Inventor： Ho-chul Ji ,  Ki-nam Kim ,  Yong-woo Hyung ,  Kyoung-won Na ,  Kyoung-ho Ha ,  Yoon-dong Park ,  Dae-lok Bae ,  Jin-kwon Bok ,  Pil-kyu Kang ,  Sung-dong Suh ,  Seong-gu Kim ,  Dong-jae Shin ,  In-sung Joe

IPC: G01J1/04

CPC classification number: G02B6/124 ,  G02B6/122 ,  G02B6/30 ,  G02B6/34 ,  G02B6/4214 ,  G02B2006/12104

Abstract: Optical waveguide and coupler devices and methods include a trench formed in a bulk semiconductor substrate, for example, a bulk silicon substrate. A bottom cladding layer is formed in the trench, and a core region is formed on the bottom cladding layer. A reflective element, such as a distributed Bragg reflector can be formed under the coupler device and/or the waveguide device. Because the optical devices are integrated in a bulk substrate, they can be readily integrated with other devices on a chip or die in accordance with silicon photonics technology. Specifically, for example, the optical devices can be integrated in a DRAM memory circuit chip die.

Abstract translation: 光波导和耦合器器件和方法包括形成在体半导体衬底中的沟槽，例如体硅衬底。 在沟槽中形成底层，在底面包层上形成芯部区域。 可以在耦合器装置和/或波导装置下形成反射元件，例如分布式布拉格反射器。 因为光学器件集成在大容量衬底中，所以它们可以根据硅光子学技术容易地与芯片上或芯片上的其它器件集成。 具体地，例如，光学器件可以集成在DRAM存储器电路芯片芯片中。

公开(公告)号：US20140035164A1

公开(公告)日：2014-02-06

申请号：US14052691

申请日：2013-10-11

Applicant: Kwang-jin Moon ,  Byung-lyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

Inventor： Kwang-jin Moon ,  Byung-lyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

IPC: H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

Abstract translation: 半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线 结构体。

公开(公告)号：US08422845B2

公开(公告)日：2013-04-16

申请号：US12968488

申请日：2010-12-15

Applicant: Pil-Kyu Kang ,  Dae Lok Bae ,  Gil Heyun Choi ,  Jong Myeong Lee

Inventor： Pil-Kyu Kang ,  Dae Lok Bae ,  Gil Heyun Choi ,  Jong Myeong Lee

IPC: G02B6/12 ,  G02B6/26 ,  G02B6/28 ,  G02B6/10 ,  G02B6/32

CPC classification number: H01L21/7624 ,  G02B6/02

Abstract: A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate.

Abstract translation: 光电集成电路器件包括一个片上光输入/输出器件。 片上光输入/输出装置包括具有沟槽的衬底，设置在沟槽中的下包层，并且具有比衬底的上表面低的上表面，以及一距离设置在下包层上的芯 从沟槽的侧壁开始并且具有与衬底的上表面基本相同的高度的上表面。

公开(公告)号：US08390120B2

公开(公告)日：2013-03-05

申请号：US12913748

申请日：2010-10-27

Applicant: Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Kwang-Jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L2224/16146 ,  H01L2225/06541 ,  H01L2924/01327 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Abstract translation: 半导体器件包括通孔结构和导电结构。 通孔结构具有平坦部分和突出部分的表面。 导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。 例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

公开(公告)号：US07781302B2

公开(公告)日：2010-08-24

申请号：US11703316

申请日：2007-02-07

Applicant: Yong-Won Cha ,  Dae-Lok Bae

Inventor： Yong-Won Cha ,  Dae-Lok Bae

IPC: H01L21/76

CPC classification number: H01L21/76243

Abstract: Methods of fabricating a semiconductor device include forming a mask pattern on a semiconductor substrate and which exposes defined regions of the semiconductor substrate. Oxygen ions are implanted into the defined regions of the semiconductor substrate using the mask pattern as an ion implantation mask. The oxygen ion implanted regions of the semiconductor substrate are annealed at one or more temperatures in a range that is sufficiently high to form silicon oxide substantially throughout the oxygen ion implanted regions by reacting the implanted oxygen ions with silicon in the oxygen ion implanted regions, and that is sufficiently low to substantially prevent oxidation of the semiconductor substrate adjacent to the oxygen ion implanted regions.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成掩模图案，并露出半导体衬底的限定区域。 使用掩模图案将氧离子注入到半导体衬底的限定区域中作为离子注入掩模。 半导体衬底的氧离子注入区域在足够高的范围内的一个或多个温度下退火，通过使注入的氧离子与氧离子注入区域中的硅反应，基本上遍及整个氧离子注入区域形成氧化硅，以及 其足够低以基本上防止邻近氧离子注入区域的半导体衬底的氧化。

公开(公告)号：US20080213982A1

公开(公告)日：2008-09-04

申请号：US12039106

申请日：2008-02-28

Applicant: Young-Soo Park ,  Young-Sam Lim ,  Young-Nam Kim ,  Dae-Lok Bae ,  Joon-Young Choi ,  Gi-Jung Kim

Inventor： Young-Soo Park ,  Young-Sam Lim ,  Young-Nam Kim ,  Dae-Lok Bae ,  Joon-Young Choi ,  Gi-Jung Kim

IPC: H01L21/36

CPC classification number: H01L21/76254 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/0262 ,  H01L21/02639

Abstract: Provided is a method of fabricating a semiconductor wafer. The method includes preparing a substrate wafer having a non-single-crystalline thin layer; disposing at least one single crystalline pattern adjacent to the non-single-crystalline thin layer on the substrate wafer; and forming a material layer contacting the single crystalline pattern on the non-single-crystalline thin layer.

Abstract translation: 提供一种制造半导体晶片的方法。 该方法包括制备具有非单晶薄层的衬底晶片; 在衬底晶片上设置与非单晶薄层相邻的至少一个单晶图案; 以及在非单晶薄层上形成与单晶图案接触的材料层。

公开(公告)号：US20140217603A1

公开(公告)日：2014-08-07

申请号：US13756593

申请日：2013-02-01

Applicant: Kwang-jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

Inventor： Kwang-jin Moon ,  Pil-Kyu Kang ,  Dae-Lok Bae ,  Gil-Heyun Choi ,  Byung-Lyul Park ,  Dong-Chan Lim ,  Deok-Young Jung

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Abstract translation: 半导体器件包括通孔结构和导电结构。 通孔结构具有平坦部分和突出部分的表面。 导电结构形成在平面部分的至少一部分上，而不是在通孔结构的突出部分的至少一部分之上。 例如，导电结构仅形成在平面部分上，而不形成在任何突出部分上，用于在导电结构和通孔结构之间形成高质量的连接。

公开(公告)号：US08354308B2

公开(公告)日：2013-01-15

申请号：US13221158

申请日：2011-08-30

Applicant: Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-lyul Park ,  Dong-kak Lee

Inventor： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-lyul Park ,  Dong-kak Lee

IPC: H01L21/336 ,  H01L21/84

CPC classification number: H01L29/66666 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203

Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

Abstract translation: 公开了一种导电层掩埋型衬底。 基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上 并且包括金属层和形成在导电层上的单晶半导体层。

公开(公告)号：US08343851B2

公开(公告)日：2013-01-01

申请号：US12585537

申请日：2009-09-17

Applicant: Jung-ho Kim ,  Dae-lok Bae ,  Jong-wook Lee ,  Seung-woo Choi ,  Pil-kyu Kang

Inventor： Jung-ho Kim ,  Dae-lok Bae ,  Jong-wook Lee ,  Seung-woo Choi ,  Pil-kyu Kang

IPC: H01L21/30 ,  H01L21/18

CPC classification number: H01L21/6835 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2224/83 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/10253 ,  H01L2924/00

Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.

Abstract translation: 使用硅直接接合（SDB）的晶片临时接合方法可以包括制备载体晶片和器件晶片，调整载体晶片的表面的粗糙度，以及使用SDB组合载体晶片和器件晶片。 因为该方法使用SDB而不是粘合剂层用于临时粘接过程，所以不需要用于产生和去除粘合剂的模块或工艺。 此外，可以防止由于粘合剂的不规则性而导致的后续工艺中的缺陷，例如后磨削工艺。