公开(公告)号：US08354308B2

公开(公告)日：2013-01-15

申请号：US13221158

申请日：2011-08-30

Applicant: Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-lyul Park ,  Dong-kak Lee

Inventor： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-lyul Park ,  Dong-kak Lee

IPC: H01L21/336 ,  H01L21/84

CPC classification number: H01L29/66666 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203

Abstract: A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

Abstract translation: 公开了一种导电层掩埋型衬底。 基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上 并且包括金属层和形成在导电层上的单晶半导体层。

公开(公告)号：US20090179252A1

公开(公告)日：2009-07-16

申请号：US12292674

申请日：2008-11-24

Applicant: Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Dong-kak Lee

Inventor： Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Dong-kak Lee

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/68

CPC classification number: H01L29/7883 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/513

Abstract: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.

Abstract translation: 闪存器件可以包括设置在衬底上的下部隧道绝缘层，设置在下部隧道绝缘层上的上部隧道绝缘层，设置在上部隧道绝缘层上的浮动栅极，设置在浮动栅极上的栅极间绝缘层; 以及设置在隔间绝缘层上的控制栅极。

公开(公告)号：US20160071946A1

公开(公告)日：2016-03-10

申请号：US14940785

申请日：2015-11-13

Applicant: Dong-Kak Lee ,  Joon Kim ,  Bong-hyun Kim ,  Han-Jin Lim

Inventor： Dong-Kak Lee ,  Joon Kim ,  Bong-hyun Kim ,  Han-Jin Lim

IPC: H01L29/49 ,  H01L27/108 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10873 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66575 ,  H01L29/78

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract translation: 公开了电极结构。 电极结构包括掺杂有电阻调节杂质的第一多晶硅层; 用于调节晶粒的第二多晶硅层，形成在第一多晶硅层中并掺杂有晶粒调节杂质; 在第一和第二多晶硅层上形成的欧姆金属层; 形成在欧姆金属层上的阻挡金属层; 以及形成在阻挡金属层上的金属层。

公开(公告)号：US20120056263A1

公开(公告)日：2012-03-08

申请号：US13225896

申请日：2011-09-06

Applicant: Dong-kak Lee ,  Hee-don Hwang

Inventor： Dong-kak Lee ,  Hee-don Hwang

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L27/10873 ,  H01L21/76232 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/7851

Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.

Abstract translation: 半导体器件包括器件隔离图案，其中掺杂有氧，碳或氮的多晶硅层图案插入在沟槽的内壁和氮化物衬垫之间。 半导体器件包括半导体衬底，其包括沟槽，沟槽表面上的多晶硅层图案，多晶硅层图案上的氮化物层图案以及氮化物层图案上的绝缘层图案并填充沟槽。 多晶硅层图案可以掺杂有氧，碳和/或氮。 还公开了相关的制造方法。

公开(公告)号：US07846836B2

公开(公告)日：2010-12-07

申请号：US12453231

申请日：2009-05-04

Applicant: Dong-Kak Lee ,  Ki-Hyun Hwang ,  Jin-Gyun Kim

Inventor： Dong-Kak Lee ,  Ki-Hyun Hwang ,  Jin-Gyun Kim

IPC: H01L21/44

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/76829 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621

Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.

Abstract translation: 在半导体器件中形成导电结构的方法包括在衬底上形成导电层，在衬底上形成导电层图案，通过图案化导电层，在衬底上形成氧化物层和导电层的一部分，以及 在氧化物层和导电层图案上形成覆盖层。

公开(公告)号：US09349821B2

公开(公告)日：2016-05-24

申请号：US14940785

申请日：2015-11-13

Applicant: Dong-Kak Lee ,  Joon Kim ,  Bong-hyun Kim ,  Han-Jin Lim

Inventor： Dong-Kak Lee ,  Joon Kim ,  Bong-hyun Kim ,  Han-Jin Lim

IPC: H01L21/311 ,  H01L21/28 ,  H01L29/49 ,  H01L27/092 ,  H01L27/108 ,  H01L29/423

CPC classification number: H01L27/092 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10873 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66575 ,  H01L29/78

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

公开(公告)号：US08766355B2

公开(公告)日：2014-07-01

申请号：US13225896

申请日：2011-09-06

Applicant: Dong-kak Lee ,  Hee-don Hwang

Inventor： Dong-kak Lee ,  Hee-don Hwang

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L27/10873 ,  H01L21/76232 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/7851

Abstract: A semiconductor device includes a device isolation pattern in which a polysilicon layer pattern doped with oxygen, carbon or nitrogen is interposed between an inner wall of a trench and a nitride liner. The semiconductor device includes a semiconductor substrate including a trench, a polysilicon layer pattern on a surface of the trench, a nitride layer pattern on the polysilicon layer pattern, and an insulation layer pattern on the nitride layer pattern and filling the trench. The polysilicon layer pattern may be doped with oxygen, carbon and/or nitrogen. Related manufacturing methods are also disclosed.

Abstract translation: 半导体器件包括器件隔离图案，其中掺杂有氧，碳或氮的多晶硅层图案插入在沟槽的内壁和氮化物衬垫之间。 半导体器件包括半导体衬底，其包括沟槽，沟槽表面上的多晶硅层图案，多晶硅层图案上的氮化物层图案以及氮化物层图案上的绝缘层图案并填充沟槽。 多晶硅层图案可以掺杂有氧，碳和/或氮。 还公开了相关的制造方法。

公开(公告)号：US08692372B2

公开(公告)日：2014-04-08

申请号：US12728396

申请日：2010-03-22

Applicant: Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

Inventor： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC: H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC classification number: H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

Abstract translation: 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US20090280615A1

公开(公告)日：2009-11-12

申请号：US12453231

申请日：2009-05-04

Applicant: Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

Inventor： Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/266

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/76829 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621

Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.

Abstract translation: 在半导体器件中形成导电结构的方法包括在衬底上形成导电层，在衬底上形成导电层图案，通过图案化导电层，在衬底上形成氧化物层和导电层的一部分，以及 在氧化物层和导电层图案上形成覆盖层。

公开(公告)号：US20080073690A1

公开(公告)日：2008-03-27

申请号：US11589789

申请日：2006-10-31

Applicant: Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Dong-kak Lee

Inventor： Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Dong-kak Lee

IPC: H01L29/76

CPC classification number: H01L29/7883 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/513

Abstract: A flash memory device may include a lower tunnel insulation layer disposed on a substrate, an upper tunnel insulation layer disposed on the lower tunnel insulation layer, a floating gate disposed on the upper tunnel insulation layer, an intergate insulation layer disposed on the floating gate; and a control gate disposed on the intergate insulation layer.

Abstract translation: 闪存器件可以包括设置在衬底上的下部隧道绝缘层，设置在下部隧道绝缘层上的上部隧道绝缘层，设置在上部隧道绝缘层上的浮动栅极，设置在浮动栅极上的栅极间绝缘层; 以及设置在隔间绝缘层上的控制栅极。