公开(公告)号：US09240357B2

公开(公告)日：2016-01-19

申请号：US14100651

申请日：2013-12-09

申请人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

发明人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC分类号： H01L21/66 ,  H01L21/265 ,  H01L21/311 ,  H01L27/115

CPC分类号： H01L22/12 ,  H01L21/31116 ,  H01L22/20 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

摘要翻译： 根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。 扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

公开(公告)号：US20150206900A1

公开(公告)日：2015-07-23

申请号：US14601496

申请日：2015-01-21

申请人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

发明人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

摘要翻译： 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US09082659B1

公开(公告)日：2015-07-14

申请号：US14643527

申请日：2015-03-10

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US09064736B2

公开(公告)日：2015-06-23

申请号：US14248003

申请日：2014-04-08

申请人： Joon-Suk Lee ,  Woong Lee ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

发明人： Joon-Suk Lee ,  Woong Lee ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

IPC分类号： H01L21/311 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region.

摘要翻译： 提供一种制造三维半导体存储器件的方法。 该方法包括在基板上交替堆叠第一绝缘膜，第一牺牲膜，交替的第二绝缘膜和第二牺牲膜，第三牺牲膜和第三绝缘膜。 形成通道孔，以在穿过第一绝缘膜，第一牺牲膜，第二绝缘膜，第二牺牲膜，第三牺牲膜和第三绝缘膜的同时暴露衬底的一部分。 该方法还包括通过外延生长在暴露在通道孔中的衬底的部分上形成半导体图案。 形成半导体图案包括形成下部外延膜，将杂质掺杂到下部外延膜中，以及在下部外延膜上形成上部外延膜。 形成下部外延膜，将杂质掺杂到下部外延膜中并形成上部外延膜全部原位进行，并且半导体图案包括掺杂区域和未掺杂区域。

公开(公告)号：US20150137210A1

公开(公告)日：2015-05-21

申请号：US14546172

申请日：2014-11-18

申请人： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

发明人： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

摘要翻译： 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

公开(公告)号：US08927366B2

公开(公告)日：2015-01-06

申请号：US13610344

申请日：2012-09-11

申请人： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

发明人： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

IPC分类号： H01L21/04 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L27/11582

摘要： A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

摘要翻译： 一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

公开(公告)号：US20140239375A1

公开(公告)日：2014-08-28

申请号：US14182325

申请日：2014-02-18

申请人： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

发明人： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

摘要翻译： 垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。 通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上依次形成在每个沟道的侧壁上。 所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。 虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

公开(公告)号：US20140084357A1

公开(公告)日：2014-03-27

申请号：US13949447

申请日：2013-07-24

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅极电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US20120276702A1

公开(公告)日：2012-11-01

申请号：US13456392

申请日：2012-04-26

申请人： Jun-kyu YANG ,  Phil-ouk Nam ,  Ki-hyun Hwang ,  Jae-young Ahn ,  Han-mei Choi ,  Bi-o Kim

发明人： Jun-kyu YANG ,  Phil-ouk Nam ,  Ki-hyun Hwang ,  Jae-young Ahn ,  Han-mei Choi ,  Bi-o Kim

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66833

摘要： A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.

摘要翻译： 制造半导体器件的方法包括形成通道区域，在沟道区域上形成缓冲层，并且通过使用含有卤素原子的气体来热处理沟道区域。

公开(公告)号：US20120129356A1

公开(公告)日：2012-05-24

申请号：US13363673

申请日：2012-02-01

申请人： Jin-Gyun KIM ,  Bon-young Koo ,  Ki-hyun Hwang

发明人： Jin-Gyun KIM ,  Bon-young Koo ,  Ki-hyun Hwang

IPC分类号： H01L21/31

CPC分类号： H01L29/4991 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4983

摘要： A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

摘要翻译： 提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。 一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙 方法。