公开(公告)号：US20070111545A1

公开(公告)日：2007-05-17

申请号：US11521145

申请日：2006-09-14

Applicant: Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim ,  Sang-ryol Yang ,  Hong-suk Kim ,  Jin-tae Noh

Inventor： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim ,  Sang-ryol Yang ,  Hong-suk Kim ,  Jin-tae Noh

IPC: H01L21/31

CPC classification number: H01L21/3141 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45525 ,  C23C16/45542 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612

Abstract: Provided herein are methods of forming a silicon dioxide layer on a substrate using an atomic layer deposition (ALD) method that include supplying a Si precursor to the substrate and forming on the substrate a Si layer including at least one Si atomic layer; and (b) supplying an oxygen radical to the Si layer to replace at least one Si—Si bond within the Si layer with a Si—O bond, thereby oxidizing the Si layer, to form a silicon dioxide layer on the substrate.

Abstract translation: 本文提供了使用原子层沉积（ALD）方法在衬底上形成二氧化硅层的方法，其包括向衬底提供Si前体并在衬底上形成包含至少一个Si原子层的Si层; 和（b）向Si层提供氧自由基以用Si-O键代替Si层内的至少一个Si-Si键，从而氧化Si层，以在衬底上形成二氧化硅层。

公开(公告)号：US08927366B2

公开(公告)日：2015-01-06

申请号：US13610344

申请日：2012-09-11

Applicant: Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

Inventor： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

IPC: H01L21/04 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11582

Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

Abstract translation: 一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

公开(公告)号：US20130089974A1

公开(公告)日：2013-04-11

申请号：US13610344

申请日：2012-09-11

Applicant: Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

Inventor： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

IPC: H01L21/04

CPC classification number: H01L27/11556 ,  H01L27/11582

Abstract: A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

Abstract translation: 一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

公开(公告)号：US08563421B2

公开(公告)日：2013-10-22

申请号：US13363673

申请日：2012-02-01

Applicant: Jin-Gyun Kim ,  Bon-young Koo ,  Ki-hyun Hwang

Inventor： Jin-Gyun Kim ,  Bon-young Koo ,  Ki-hyun Hwang

IPC: H01L21/4763

CPC classification number: H01L29/4991 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4983

Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

Abstract translation: 提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。 一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙 方法。

公开(公告)号：US20120129356A1

公开(公告)日：2012-05-24

申请号：US13363673

申请日：2012-02-01

Applicant: Jin-Gyun KIM ,  Bon-young Koo ,  Ki-hyun Hwang

Inventor： Jin-Gyun KIM ,  Bon-young Koo ,  Ki-hyun Hwang

IPC: H01L21/31

CPC classification number: H01L29/4991 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4983

Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

Abstract translation: 提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。 一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙 方法。

公开(公告)号：US08129264B2

公开(公告)日：2012-03-06

申请号：US12181166

申请日：2008-07-28

Applicant: Jin-Gyun Kim ,  Bon-young Koo ,  Ki-hyun Hwang

Inventor： Jin-Gyun Kim ,  Bon-young Koo ,  Ki-hyun Hwang

IPC: H01L21/4763

CPC classification number: H01L29/4991 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4983

Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

Abstract translation: 提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。 一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙 方法。

公开(公告)号：US20120001264A1

公开(公告)日：2012-01-05

申请号：US13173360

申请日：2011-06-30

Applicant: Hong-suk Kim ,  Jin-gyun Kim ,  Hun-Hyeong Lim ,  Ki-hyun Hwang ,  Jae-Young Ahn ,  Jun-kyu Yang

Inventor： Hong-suk Kim ,  Jin-gyun Kim ,  Hun-Hyeong Lim ,  Ki-hyun Hwang ,  Jae-Young Ahn ,  Jun-kyu Yang

IPC: H01L21/28 ,  C09K13/04 ,  H01L27/088

CPC classification number: C09K13/04 ,  H01L21/764 ,  H01L21/823437 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

Abstract: Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided.

Abstract translation: 根据本发明的实施例提供的是使用蚀刻剂制造半导体器件的方法。 在一些实施例中，蚀刻剂可以是高度选择性的并且可以用于减小半导体器件中的字线之间的干扰。 在本发明的一些实施例中，提供了制造半导体器件的方法，该半导体器件包括在衬底上形成多个栅极图案; 在栅极图案之间形成第一绝缘层; 湿蚀刻第一绝缘层以形成第一绝缘层残留物; 以及在所述多个栅极图案之间形成气隙。 还提供了相关蚀刻剂溶液和半导体器件。

公开(公告)号：US20090042383A1

公开(公告)日：2009-02-12

申请号：US12181166

申请日：2008-07-28

Applicant: JIN GYUN KIM ,  Bon-young Koo ,  Ki-hyun Hwang

Inventor： JIN GYUN KIM ,  Bon-young Koo ,  Ki-hyun Hwang

IPC: H01L21/4763

CPC classification number: H01L29/4991 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/4983

Abstract: A method of forming a dielectric layer having an air gap to isolate adjacent wirings or a gate stack of the semiconductor device is provided. A method of fabricating a semiconductor device includes providing a semiconductor substrate on which a plurality of wirings are formed adjacent to one another and forming a dielectric layer filling an upper portion of a space between the adjacent wirings to form air gaps by a thermal chemical vapor deposition method.

Abstract translation: 提供一种形成具有气隙以隔离相邻配线或半导体器件的栅极叠层的电介质层的方法。 一种制造半导体器件的方法包括提供半导体衬底，多个布线彼此相邻地形成有多个布线，并形成填充相邻布线之间的空间的上部的介电层，以通过热化学气相沉积形成空隙 方法。

公开(公告)号：US20080128788A1

公开(公告)日：2008-06-05

申请号：US12003992

申请日：2008-01-04

Applicant: Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Jin-tae Noh

Inventor： Sung-kweon Baek ,  Sang-ryol Yang ,  Si-young Choi ,  Bon-young Koo ,  Ki-hyun Hwang ,  Jin-tae Noh

IPC: H01L29/68 ,  H01L29/788 ,  H01L21/04

CPC classification number: H01L29/513 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Abstract translation: 一种闪存装置，包括在基板上的下部隧道绝缘层，下部隧道绝缘层上的上部隧道绝缘层和上部隧道绝缘层上的P型栅极，其中上部隧道绝缘层包括无定形氧化物层 。

公开(公告)号：US08617947B2

公开(公告)日：2013-12-31

申请号：US13456392

申请日：2012-04-26

Applicant: Jun-kyu Yang ,  Phil-ouk Nam ,  Ki-hyun Hwang ,  Jae-young Ahn ,  Han-mei Choi ,  Bi-o Kim

Inventor： Jun-kyu Yang ,  Phil-ouk Nam ,  Ki-hyun Hwang ,  Jae-young Ahn ,  Han-mei Choi ,  Bi-o Kim

IPC: H01L21/8238

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66833

Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.

Abstract translation: 制造半导体器件的方法包括形成通道区域，在沟道区域上形成缓冲层，并且通过使用含有卤素原子的气体来热处理沟道区域。