公开(公告)号：US20150137210A1

公开(公告)日：2015-05-21

申请号：US14546172

申请日：2014-11-18

申请人： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

发明人： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

IPC分类号： H01L27/115 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

摘要翻译： 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

公开(公告)号：US20140239375A1

公开(公告)日：2014-08-28

申请号：US14182325

申请日：2014-02-18

申请人： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

发明人： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

摘要翻译： 垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。 通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上依次形成在每个沟道的侧壁上。 所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。 虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

公开(公告)号：US20150279955A1

公开(公告)日：2015-10-01

申请号：US14644408

申请日：2015-03-11

申请人： Eun-Yeoung CHOI ,  Young-Jin NOH ,  Bi-O KIM ,  Kwang-Min PARK ,  Jae-Young AHN ,  Ju-Mi YUN ,  Jae-Ho CHOI ,  Ki-Hyun HWANG

发明人： Eun-Yeoung CHOI ,  Young-Jin NOH ,  Bi-O KIM ,  Kwang-Min PARK ,  Jae-Young AHN ,  Ju-Mi YUN ,  Jae-Ho CHOI ,  Ki-Hyun HWANG

IPC分类号： H01L29/51 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/518

摘要： Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

摘要翻译： 公开了隧道绝缘层结构及其制造方法。 隧道绝缘层结构可以包括第一隧道绝缘层，第二隧道绝缘层，第三隧道绝缘层，第四隧道绝缘层和第五隧道绝缘层。 衬底上的第一隧道绝缘层具有第一带隙能量。 第一隧道绝缘层上的第二隧道绝缘层具有低于第一带隙能量的第二带隙能量。 第二隧道绝缘层上的第三隧道绝缘层具有高于第二带隙能量的第三带隙能量。 第三隧道绝缘层上的第四隧道绝缘层具有低于第三带隙能量的第四带隙能量。 第四隧道绝缘层上的第五隧道绝缘层具有比第四带隙能量高的第五带隙能量。

公开(公告)号：US20070048957A1

公开(公告)日：2007-03-01

申请号：US11468944

申请日：2006-08-31

申请人： Sung-Hae LEE ,  Ju-Wan LIM ,  Jae-Young AHN ,  Sang-Ryol YANG ,  Ki-Hyun HWANG

发明人： Sung-Hae LEE ,  Ju-Wan LIM ,  Jae-Young AHN ,  Sang-Ryol YANG ,  Ki-Hyun HWANG

IPC分类号： H01L21/8228

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/4234 ,  Y10S438/954

摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.

摘要翻译： 在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层 。 通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。 在氮化硅层上形成第二氧化物层。 因此，形成具有良好擦除特性的电荷俘获电介质。 在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

公开(公告)号：US20150206900A1

公开(公告)日：2015-07-23

申请号：US14601496

申请日：2015-01-21

申请人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

发明人： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

摘要： A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

摘要翻译： 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US20110053365A1

公开(公告)日：2011-03-03

申请号：US12942107

申请日：2010-11-09

申请人： Ki-Hyun HWANG ,  Won-Jun JANG ,  Jae-Young AHN ,  Chang-Sup MUN ,  Jung-Hyun PARK

发明人： Ki-Hyun HWANG ,  Won-Jun JANG ,  Jae-Young AHN ,  Chang-Sup MUN ,  Jung-Hyun PARK

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： B82Y10/00 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/115 ,  H01L27/11521

摘要： In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.

摘要翻译： 在半导体装置的制造方法中，在基板上形成氧化硅层。 氧化硅层用包含臭氧的溶液处理。 然后，在用该溶液处理的氧化硅层上形成导电层。

公开(公告)号：US20100210116A1

公开(公告)日：2010-08-19

申请号：US12704299

申请日：2010-02-11

申请人： Jae-Young AHN ,  Ki-Hyun Hwang ,  Young-Geun Park ,  Jun-Kyu Yang ,  Byong-Sun Ju ,  Dong-Woon Shin

发明人： Jae-Young AHN ,  Ki-Hyun Hwang ,  Young-Geun Park ,  Jun-Kyu Yang ,  Byong-Sun Ju ,  Dong-Woon Shin

IPC分类号： H01L21/461

CPC分类号： H01L21/76837 ,  C23C16/045 ,  C23C16/45542 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228

摘要： A method of forming a vapor thin film is provided, which includes loading a substrate into a chamber, adsorbing a source gas on the substrate by supplying the source gas into the chamber, and forming the thin film on the substrate by supplying a reaction gas into the chamber, wherein the forming of the thin film on the substrate is proceeded under an electric field formed in one direction on the substrate by applying a bias to the substrate.

摘要翻译： 提供一种形成蒸气薄膜的方法，其包括将基板装载到室中，通过将源气体供应到室中来将源气体吸附在基板上，并通过将反应气体供应到基板上而形成薄膜 其中，通过向衬底施加偏压，在衬底上的薄膜的形成在基板上沿一个方向形成的电场上进行。

公开(公告)号：US20140322832A1

公开(公告)日：2014-10-30

申请号：US14100651

申请日：2013-12-09

申请人： Tae-Gon KIM ,  Jong-Hoon KANG ,  Jae-Young AHN ,  Jun-Kyu YANG ,  Han-Mei CHOI ,  Ki-Hyun HWANG

发明人： Tae-Gon KIM ,  Jong-Hoon KANG ,  Jae-Young AHN ,  Jun-Kyu YANG ,  Han-Mei CHOI ,  Ki-Hyun HWANG

IPC分类号： H01L21/66 ,  H01L21/3065

CPC分类号： H01L22/12 ,  H01L21/31116 ,  H01L22/20 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

摘要翻译： 根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。 扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

公开(公告)号：US20160168704A1

公开(公告)日：2016-06-16

申请号：US14963744

申请日：2015-12-09

申请人： Ji-Hoon CHOI ,  Young-Jin NOH ,  Joong-Yun RA ,  Jae-Young AHN ,  Hun-hyeong LIM

发明人： Ji-Hoon CHOI ,  Young-Jin NOH ,  Joong-Yun RA ,  Jae-Young AHN ,  Hun-hyeong LIM

IPC分类号： C23C16/455

CPC分类号： C23C16/45578 ,  C23C16/45546

摘要： A gas injector may comprise: a gas introduction tube configured to introduce reaction gas into a reaction tube from a gas supply source; and/or a gas distributor connected to the gas introduction tube, extending from the gas introduction tube in a direction within the reaction tube, including a plurality of ejection holes in an inner surface of the gas distributor, and having an arc shape extending in a circumferential direction of the reaction tube. The ejection holes may be spaced apart from each other in the extending direction of the gas distributor, and are configured to spray the reaction gas.

摘要翻译： 气体注入器可以包括：气体引入管，其构造成将反应气体从气体供应源引入反应管中; 和/或气体分配器，其连接到气体导入管，从气体导入管沿着反应管内的方向延伸，包括在气体分配器的内表面中的多个喷射孔，并且具有在 反应管的圆周方向。 喷射孔可以在气体分配器的延伸方向上彼此间隔开，并且被配置为喷射反应气体。

公开(公告)号：US20180122822A1

公开(公告)日：2018-05-03

申请号：US15610923

申请日：2017-06-01

申请人： Joon-Suk LEE ,  Hong-Suk KIM ,  Jae-Young AHN ,  Han-Jin LIM

发明人： Joon-Suk LEE ,  Hong-Suk KIM ,  Jae-Young AHN ,  Han-Jin LIM

IPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/10

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/1045 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.