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    Methods of fabricating memory devices using wet etching and dry etching
    2.
    发明授权
    Methods of fabricating memory devices using wet etching and dry etching 有权
    使用湿蚀刻和干蚀刻制造存储器件的方法

    公开(公告)号：US09484219B2

    公开(公告)日：2016-11-01

    申请号：US14826845

    申请日：2015-08-14

    Applicant: Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

    Inventor： Young-Geun Park ,  Wook-Yeol Yi ,  Sang-Yeol Kang ,  Dong-Chan Kim ,  Chang-Mu An ,  Bong-Hyun Kim ,  Han-Jin Lim

    IPC: H01L21/8242 ,  H01L21/311 ,  H01L27/108

    CPC classification number: H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

    Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

    Abstract translation: 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

    Semiconductor device and fabricating method thereof
    3.
    发明授权
    Semiconductor device and fabricating method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US09287270B2

    公开(公告)日：2016-03-15

    申请号：US14279301

    申请日：2014-05-15

    Applicant: Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    Inventor： Jung-Hwan Oh ,  Hyun-Jun Kim ,  Jong-Bom Seo ,  Ki-Vin Im ,  Han-Jin Lim

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10805 ,  H01L27/10808 ,  H01L27/1085 ,  H01L28/91

    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

    Abstract translation: 提供一种半导体器件及其制造方法。 半导体器件包括具有圆柱形状的存储电极，形成在存储电极上的电介质膜和形成在电介质膜上的平板电极，其中该平板电极包括一个第一半导体化合物层和第二半导体化合物层， 另一方面，第一半导体化合物层的结晶度与第二半导体化合物层的结晶度不同。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160064386A1

    公开(公告)日：2016-03-03

    申请号：US14826845

    申请日：2015-08-14

    Applicant: Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

    Inventor： Young-Geun PARK ,  Wook-Yeol YI ,  Sang-Yeol KANG ,  Dong-Chan KIM ,  Chang-Mu AN ,  Bong-Hyun KIM ,  Han-Jin LIM

    IPC: H01L27/108 ,  H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/31111 ,  H01L21/31116 ,  H01L27/10852 ,  H01L27/10855

    Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

    Abstract translation: 制造半导体器件的方法可以包括在下层上形成模具结构，所述模具结构包括以第一杂质浓度掺杂的蚀刻停止层，以第二杂质浓度掺杂的下模层和未掺杂的上模层。 该方法可以包括使用干蚀刻形成在模具结构中暴露下层的沟槽，使用湿蚀刻在蚀刻停止层中延伸沟槽的宽度，以及在扩展宽度沟槽中形成第一导电图案，其中蚀刻速率 相对于干蚀刻的蚀刻停止层的蚀刻速度可以小于相对于干蚀刻的下模层的蚀刻速率，并且蚀刻停止层相对于湿蚀刻的蚀刻速率可以与 第一杂质浓度。

    Semiconductor devices having self-aligned contact pads
    6.
    发明授权
    Semiconductor devices having self-aligned contact pads 有权
    具有自对准接触焊盘的半导体器件

    公开(公告)号：US09240414B1

    公开(公告)日：2016-01-19

    申请号：US14875396

    申请日：2015-10-05

    Applicant: Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    Inventor： Young-Kuk Kim ,  Ki-Vin Im ,  Han-Jin Lim ,  In-Seak Hwang

    IPC: H01L21/336 ,  H01L27/108 ,  H01L29/78 ,  H01L29/423

    CPC classification number: H01L27/10823 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/60 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7827

    Abstract: A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.

    Abstract translation: 半导体器件包括具有限定有源区域的场区域的衬底，衬底中的栅极沟槽和沿第一方向延伸的衬底，相应栅极沟槽中的掩埋栅极，在相应的掩埋栅极上的相应栅极沟槽中的栅极栅极栅极， 所述栅极覆盖栅栏从所述有源区域的顶表面突出并且沿所述第一方向延伸，所述栅极覆盖栅栏中的位线沟槽跨过所述栅极覆盖栅栏并沿垂直于所述第一方向的第二方向延伸的相应位线沟槽， 相应位线沟槽的内壁上的绝缘体结构，堆叠在相应位线沟槽中的绝缘体结构上的位线和位线封接图案，与栅极覆盖栅栏自对准的接触焊盘和相邻位之间的衬底上的绝缘体结构 线路和相应接触焊盘上的电容器的下电极。

    Storage electrode of a semiconductor memory device
    10.
    发明授权
    Storage electrode of a semiconductor memory device 有权
    半导体存储器件的存储电极

    公开(公告)号：US06809363B2

    公开(公告)日：2004-10-26

    申请号：US10418090

    申请日：2003-04-18

    Applicant: Young Sub Yu ,  Seok Sik Kim ,  Ki Hyun Hwang ,  Han Jin Lim ,  Sung Je Choi

    Inventor： Young Sub Yu ,  Seok Sik Kim ,  Ki Hyun Hwang ,  Han Jin Lim ,  Sung Je Choi

    IPC: H01L21108

    CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10855

    Abstract: A storage electrode has a truncated-conical “pipe-shaped” top section having a small inner diameter, mounted on a cylindrical base section having a large inner diameter. To fabricate the storage electrode, a buried contact plug is formed on a first insulating layer on a wafer, and an etching stop layer and a second insulating layer are formed on the first insulating layer. A third insulating layer is formed on the second insulating layer after implanting impurities into the second insulating layer. An opening is formed by anisotropically etching the third insulating layer and the second insulating layer using a photoresist pattern as an etching mask. A cleaning process is carried out such that the second insulating layer exposed through the opening is isotropically etched. After depositing polysilicon along a profile of the second and third insulating layers to a uniform thickness, the remaining third and second insulating layers are removed.

    Abstract translation: 存储电极具有安装在具有大内径的圆筒形基部上的具有小内径的截头圆锥形“管状”顶部部分。 为了制造存储电极，在晶片上的第一绝缘层上形成掩埋接触插塞，在第一绝缘层上形成蚀刻停止层和第二绝缘层。 在将杂质注入第二绝缘层之后，在第二绝缘层上形成第三绝缘层。 通过使用光致抗蚀剂图案作为蚀刻掩模对第三绝缘层和第二绝缘层进行各向异性蚀刻来形成开口。 进行清洁处理，使得通过开口暴露的第二绝缘层被各向同性地蚀刻。 沿着第二和第三绝缘层的轮廓将多晶硅沉积到均匀的厚度之后，剩余的第三和第二绝缘层被去除。

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