公开(公告)号：US20090280615A1

公开(公告)日：2009-11-12

申请号：US12453231

申请日：2009-05-04

Applicant: Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

Inventor： Dong-Kak LEE ,  Ki-Hyun HWANG ,  Jin-Gyun KIM

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/266

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  H01L21/76829 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621

Abstract: A method of forming a conductive structure in a semiconductor device includes forming a conductive layer on a substrate, forming a conductive layer pattern on the substrate by patterning the conductive layer, forming an oxide layer on the substrate and a portion of the conductive layer, and forming a capping layer on the oxide layer and the conductive layer pattern.

Abstract translation: 在半导体器件中形成导电结构的方法包括在衬底上形成导电层，在衬底上形成导电层图案，通过图案化导电层，在衬底上形成氧化物层和导电层的一部分，以及 在氧化物层和导电层图案上形成覆盖层。

公开(公告)号：US20130273704A1

公开(公告)日：2013-10-17

申请号：US13716859

申请日：2012-12-17

Applicant: Jung-Geun JEE ,  Jin-Gyun KIM ,  Ji-Hoon CHOI ,  Ki-Hyun HWANG

Inventor： Jung-Geun JEE ,  Jin-Gyun KIM ,  Ji-Hoon CHOI ,  Ki-Hyun HWANG

IPC: H01L21/36 ,  H01L29/66

CPC classification number: H01L21/36 ,  C23C16/24 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/76876 ,  H01L21/76877 ,  H01L27/10888 ,  H01L27/11582 ,  H01L29/66666

Abstract: A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

Abstract translation: 形成多晶硅层的方法包括将硅前体提供到加载在处理室中的物体上以形成种子层。 硅前体包括含氮的硅前体和含氯的硅前体。 该方法还包括在种子层上提供硅源。

公开(公告)号：US20150137210A1

公开(公告)日：2015-05-21

申请号：US14546172

申请日：2014-11-18

Applicant: Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

Inventor： Phil-Ouk NAM ,  Jun-Kyu YANG ,  Jin-Gyun KIM ,  Jae-Young AHN ,  Hun Hyeong LIM ,  Ki-Hyun HWANG

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

Abstract translation: 制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道， 蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

公开(公告)号：US20140239375A1

公开(公告)日：2014-08-28

申请号：US14182325

申请日：2014-02-18

Applicant: Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

Inventor： Jin-Gyun KIM ,  Jae-Young AHN ,  Ki-Hyun HWANG

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

Abstract: A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

Abstract translation: 垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。 通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上依次形成在每个沟道的侧壁上。 所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。 虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

公开(公告)号：US20120153291A1

公开(公告)日：2012-06-21

申请号：US13298728

申请日：2011-11-17

Applicant: Jin-Gyun KIM ,  Ki-Hyun HWANG ,  Sung-Hae LEE ,  Ji-Hoon CHOI

Inventor： Jin-Gyun KIM ,  Ki-Hyun HWANG ,  Sung-Hae LEE ,  Ji-Hoon CHOI

IPC: H01L29/792 ,  H01L29/04

CPC classification number: H01L29/7926 ,  H01L27/11582 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/7923

Abstract: A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.

Abstract translation: 垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。 第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。 此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。 半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。 此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。 还讨论了相关方法。

公开(公告)号：US20130334593A1

公开(公告)日：2013-12-19

申请号：US13972533

申请日：2013-08-21

Applicant: Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

Inventor： Kwang-Soo SEOL ,  Chanjin PARK ,  Ki-Hyun HWANG ,  Hanmei CHOI ,  Sunghoi HUR ,  Wansik HWANG ,  Toshiro NAKANISHI ,  Kwangmin PARK ,  Ju-Yul LEE

IPC: H01L29/792

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US20150206900A1

公开(公告)日：2015-07-23

申请号：US14601496

申请日：2015-01-21

Applicant: Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

Inventor： Phil-Ouk NAM ,  Dong-Chul YOO ,  Bi-O KIM ,  Jae-Young AHN ,  Byong-Hyun JANG ,  Ki-Hyun HWANG

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157

Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

Abstract translation: 一种垂直存储器件，包括：包括第一区域和第二区域的衬底; 所述第一区域中的多个通道，所述多个通道在基本上垂直于所述基板的顶表面的第一方向上延伸; 每个通道的侧壁上的电荷存储结构，其基本上平行于所述基板的顶表面; 所述第一区域中的多个栅极电极，所述多个栅电极设置在所述电荷存储结构的侧壁上，并且在所述第一方向上彼此间隔开; 以及在所述第二区域中的多个支撑件，所述多个支撑件在基本上垂直于所述第一方向和所述第二方向的第三方向上彼此间隔开，所述多个支撑件接触至少一个栅电极的侧壁。

公开(公告)号：US20110053365A1

公开(公告)日：2011-03-03

申请号：US12942107

申请日：2010-11-09

Applicant: Ki-Hyun HWANG ,  Won-Jun JANG ,  Jae-Young AHN ,  Chang-Sup MUN ,  Jung-Hyun PARK

Inventor： Ki-Hyun HWANG ,  Won-Jun JANG ,  Jae-Young AHN ,  Chang-Sup MUN ,  Jung-Hyun PARK

IPC: H01L21/28 ,  H01L21/3205

CPC classification number: B82Y10/00 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/115 ,  H01L27/11521

Abstract: In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.

Abstract translation: 在半导体装置的制造方法中，在基板上形成氧化硅层。 氧化硅层用包含臭氧的溶液处理。 然后，在用该溶液处理的氧化硅层上形成导电层。

公开(公告)号：US20150155297A1

公开(公告)日：2015-06-04

申请号：US14315906

申请日：2014-06-26

Applicant: Dae-hong EOM ,  Dong-Chul YOO ,  Kyung-Hyun KIM ,  Ki-Hyun HWANG

Inventor： Dae-hong EOM ,  Dong-Chul YOO ,  Kyung-Hyun KIM ,  Ki-Hyun HWANG

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7926

Abstract: Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap.

Abstract translation: 提供一种制造半导体存储器件的方法。 该方法包括在衬底上交替堆叠层间绝缘层和牺牲层，形成通过层间绝缘层和牺牲层暴露衬底的沟道孔，在其上依次形成阻挡绝缘层，电荷存储层和沟道层 衬底暴露在通道孔的侧壁和通道孔中，其中阻挡绝缘层包括第一阻挡绝缘层和第二阻挡绝缘层，选择性地去除牺牲层以暴露第一阻挡绝缘层，然后形成间隙， 去除在所述间隙中暴露的所述第一阻挡绝缘层，在所述层间绝缘层和所述第二阻挡绝缘层之间形成第一阻挡绝缘图案，以及在所述间隙中形成栅电极。

公开(公告)号：US20150104916A1

公开(公告)日：2015-04-16

申请号：US14248003

申请日：2014-04-08

Applicant: Joon-Suk Lee ,  Woong LEE ,  Hun-Hyeong LIM ,  Ki-Hyun HWANG

Inventor： Joon-Suk Lee ,  Woong LEE ,  Hun-Hyeong LIM ,  Ki-Hyun HWANG

IPC: H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region.

Abstract translation: 提供一种制造三维半导体存储器件的方法。 该方法包括在基板上交替堆叠第一绝缘膜，第一牺牲膜，交替的第二绝缘膜和第二牺牲膜，第三牺牲膜和第三绝缘膜。 形成通道孔，以在穿过第一绝缘膜，第一牺牲膜，第二绝缘膜，第二牺牲膜，第三牺牲膜和第三绝缘膜的同时暴露衬底的一部分。 该方法还包括通过外延生长在暴露在通道孔中的衬底的部分上形成半导体图案。 形成半导体图案包括形成下部外延膜，将杂质掺杂到下部外延膜中，以及在下部外延膜上形成上部外延膜。 形成下部外延膜，将杂质掺杂到下部外延膜中并形成上部外延膜全部原位进行，并且半导体图案包括掺杂区域和未掺杂区域。