公开(公告)号：US07910909B2

公开(公告)日：2011-03-22

申请号：US12232745

申请日：2008-09-23

申请人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

发明人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： H01L45/00

CPC分类号： H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

摘要： Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.

摘要翻译： 提供了可以被配置为堆叠结构并且可以更容易地高度集成的非易失性存储器件，以及制造非易失性存储器件的方法。 提供至少一个第一电极和至少一个第二电极。 所述至少一个第二电极可以穿过所述至少一个第一电极。 至少一个数据存储层可以在至少一个第一电极和至少一个第二电极之间的交叉点处。 所述至少一个第一电极和所述至少一个第二电极中的任何一个可以包括连接到所述至少一个数据存储层的至少一个结二极管。

公开(公告)号：US07833890B2

公开(公告)日：2010-11-16

申请号：US12457366

申请日：2009-06-09

申请人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

发明人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US20090253255A1

公开(公告)日：2009-10-08

申请号：US12457366

申请日：2009-06-09

申请人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

发明人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07585755B2

公开(公告)日：2009-09-08

申请号：US11978567

申请日：2007-10-30

申请人： Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

发明人： Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

IPC分类号： H01L21/8239 ,  H01L29/788 ,  H01L29/792 ,  H01L27/105

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。 多个下电荷存储层可以形成在半导体层的底表面上。 可以在多个下电荷存储层上形成多个下控制栅电极。 多个上电荷存储层可以形成在半导体层的顶表面上。 多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

公开(公告)号：US07551491B2

公开(公告)日：2009-06-23

申请号：US11715404

申请日：2007-03-08

申请人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

发明人： Won-joo Kim ,  Suk-pil Kim ,  Jae-woong Hyun ,  Yoon-dong Park ,  June-mo Koo

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0491 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.

摘要翻译： 提供非易失性存储器件的单元电池及其方法。 在一个示例中，单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管，第一和第二存储晶体管分别包括第一和第二存储节点， 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中，单元可以包括其中限定了第一和第二位线区域的半导体衬底，分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层，形成的第一遍栅极电极 在第一位线区域和第一存储节点层之间的半导体衬底上，形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极，形成在半导体衬底上的第三栅极电极 在所述第一和第二存储节点层之间形成第三位线区域，所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中，以及跨越所述第一和第二存储节点层延伸的控制栅电极。 示例性单元单元可以在非易失性存储器件（例如，闪存器件）内实现，使得非易失性存储器件可以包括多个示例单位单元。

公开(公告)号：US20080111199A1

公开(公告)日：2008-05-15

申请号：US11976004

申请日：2007-10-19

申请人： Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

发明人： Suk-pil KIM ,  Yoon-dong Park ,  Jong-Jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07948024B2

公开(公告)日：2011-05-24

申请号：US12484339

申请日：2009-06-15

申请人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

发明人： Suk-pil Kim ,  Yoon-dong Park ,  June-mo Koo ,  Tae-eung Yoon

IPC分类号： H01L21/336

CPC分类号： H01L27/11556 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11578

摘要： A nonvolatile memory device is provided that includes; a first semiconductor layer extending in a first direction, a second semiconductor layer extending in parallel with and separated from the first semiconductor layer, an isolation layer between the first semiconductor layer and second semiconductor layer, a first control gate electrode between the first semiconductor layer and the isolation layer, a second control gate electrode between the second semiconductor layer and the isolation layer, wherein the second control gate electrode and first control gate electrode are respectively disposed at opposite sides of the isolation layer, a first charge storing layer between the first control gate electrode and the first semiconductor layer, and a second charge storing layer between the second control gate electrode and the second semiconductor layer.

摘要翻译： 提供了一种非易失性存储装置，包括： 沿第一方向延伸的第一半导体层，与第一半导体层平行延伸并与第一半导体层分离的第二半导体层，在第一半导体层和第二半导体层之间的隔离层，第一半导体层与第一半导体层之间的第一半导体层， 所述隔离层，所述第二半导体层和所述隔离层之间的第二控制栅极电极，其中所述第二控制栅极电极和所述第一控制栅电极分别设置在所述隔离层的相对侧，所述第一控制栅极之间的第一电荷存储层 栅电极和第一半导体层，以及在第二控制栅电极和第二半导体层之间的第二电荷存储层。

公开(公告)号：US07932551B2

公开(公告)日：2011-04-26

申请号：US11902511

申请日：2007-09-21

申请人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

发明人： Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Sung-jae Byun

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66803

摘要： A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.

摘要翻译： 提供非易失性存储器件。 在非易失性存储器件中，第一导电类型的半导体衬底包括第一和第二鳍片。 公共位线电极将第一鳍片的一端连接到第二鳍片的一端。 控制栅电极覆盖第一和第二鳍片并且横跨第一和第二鳍片中的每一个的顶表面扩展。 位于公共位线电极和控制栅电极之间的第一串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。 位于第一串选择栅极电极和控制栅电极之间的第二串选择栅电极可以覆盖第一和第二散热片并且横跨第一和第二散热片的每一个的顶表面膨胀。

公开(公告)号：US07894265B2

公开(公告)日：2011-02-22

申请号：US12081679

申请日：2008-04-18

申请人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

发明人： Tae-hee Lee ,  Won-joo Kim ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Tae-eung Yoon

IPC分类号： G11C5/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/0483 ,  H01L27/11521 ,  H01L27/11568

摘要： The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor. A method of programming a target cell of the memory device includes activating selection transistors connected to a main string and substring of the target cell.

摘要翻译： 非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。 编程存储器件的目标单元的方法包括激活连接到目标单元的主串和子串的选择晶体管。

公开(公告)号：US07829932B2

公开(公告)日：2010-11-09

申请号：US11980632

申请日：2007-10-31

申请人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

发明人： Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Won-joo Kim ,  June-mo Koo ,  Kyoung-Iae Cho ,  Jae-woong Hyun ,  Sung-jae Byun

IPC分类号： H01L29/788

CPC分类号： H01L29/785 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7881 ,  H01L29/792 ,  H01L2029/7858

摘要： Example embodiments relate to a semiconductor device including a fin-type channel region and a method of fabricating the same. The semiconductor device includes a semiconductor substrate, a semiconductor pillar and a contact plug. The semiconductor substrate includes at least one pair of fins used (or functioning) as an active region. The semiconductor pillar may be interposed between portions of the fins to connect the fins. The contact plug may be disposed (or formed) on the semiconductor pillar and electrically connected to top surfaces of the fins.

摘要翻译： 示例性实施例涉及包括鳍型沟道区的半导体器件及其制造方法。 半导体器件包括半导体衬底，半导体柱和接触插塞。 半导体衬底包括至少一对使用（或功能）作为活性区的翅片。 半导体柱可以插入翅片的部分之间以连接散热片。 接触插塞可以设置（或形成）在半导体柱上并电连接到散热片的顶表面。