公开(公告)号：US07718475B2

公开(公告)日：2010-05-18

申请号：US11786822

申请日：2007-04-13

Applicant: Matthias Goldbach ,  Erhard Landgraf ,  Michael Stadtmueller ,  Moritz Haupt ,  Sven Schmidbauer ,  Tobias Mono ,  Jorg Radecker

Inventor： Matthias Goldbach ,  Erhard Landgraf ,  Michael Stadtmueller ,  Moritz Haupt ,  Sven Schmidbauer ,  Tobias Mono ,  Jorg Radecker

IPC: H01L21/335 ,  H01L29/76

CPC classification number: H01L21/28061 ,  H01L29/4941 ,  H01L29/78 ,  H01L29/7845

Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract translation: 本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

公开(公告)号：US07679149B2

公开(公告)日：2010-03-16

申请号：US11669500

申请日：2007-01-31

Applicant: Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

Inventor： Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

IPC: H01L29/76

CPC classification number: H01L21/28518 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.

Abstract translation: 公开了一种与硅化钴形成接触的方法。 例如，在用SOM溶液硅化后，例如包括例如作为硅化的初始层的钴的钴的沉积层的未反应部分和包括钛并通过阴极射线溅射沉积的氧化保护层可以是 相对于硅化钴和其它致密的金属结构和金属层，快速且高选择性地去除。

公开(公告)号：US20080116494A1

公开(公告)日：2008-05-22

申请号：US11602066

申请日：2006-11-20

Applicant: Matthias Goldbach ,  Dietmar Henke ,  Sven Schmidbauer

Inventor： Matthias Goldbach ,  Dietmar Henke ,  Sven Schmidbauer

IPC: H01L29/76 ,  H01L21/265 ,  H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/265 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a method for manufacturing a semiconductor device. A silicon substrate comprising at least one structured area in which a dopant is implanted is provided. A contact modifying material is provided on the surface of the at least one structured area. A silicide layer is formed on the surface of the at least one structured area, the silicide layer comprising at least one of titan silicide, titan nitride silicide and cobalt silicide.

Abstract translation: 本发明涉及半导体器件的制造方法。 提供了包括其中注入掺杂剂的至少一个结构化区域的硅衬底。 接触改性材料设置在至少一个结构化区域的表面上。 在所述至少一个结构化区域的表面上形成硅化物层，所述硅化物层包括硅化钛，氮化钛硅化物和硅化钴中的至少一种。

公开(公告)号：US07192830B2

公开(公告)日：2007-03-20

申请号：US10862818

申请日：2004-06-07

Applicant: Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

Inventor： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

IPC: H01L21/336

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

Abstract: Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

Abstract translation: 将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。 通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。 存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。 该存储单元适合作为虚拟地面架构中的多位闪存单元。

公开(公告)号：US07183156B2

公开(公告)日：2007-02-27

申请号：US10975085

申请日：2004-10-28

Applicant: Matthias Goldbach ,  Ulrich Frey ,  Björn Fischer

Inventor： Matthias Goldbach ,  Ulrich Frey ,  Björn Fischer

IPC: H01L21/8242

CPC classification number: H01L27/10888 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/42368

Abstract: Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

Abstract translation: 晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。 在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。 对于栅极导体结构的相同特征尺寸，有效沟道长度增加。 可以以更高的密度实现存储单元。

公开(公告)号：US20060275981A1

公开(公告)日：2006-12-07

申请号：US11442602

申请日：2006-05-30

Applicant: Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

Inventor： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

IPC: H01L21/8242 ,  H01L29/94

CPC classification number: H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

Abstract translation: 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。

公开(公告)号：US20060226473A1

公开(公告)日：2006-10-12

申请号：US11101378

申请日：2005-04-07

Applicant: Dongping Wu ,  Matthias Goldbach ,  Ulrich Egger

Inventor： Dongping Wu ,  Matthias Goldbach ,  Ulrich Egger

IPC: H01L29/792

CPC classification number: H01L21/28061 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76897 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/517

Abstract: A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection is enabled.

Abstract translation: 栅电极堆叠设置在半导体器件中的衬底上。 栅极导体包括至少一层多晶硅和至少一层多晶Si 1-x N，Ge x S x材料。 本发明也涉及一个过程。 可以有效地蚀刻这种结构，因为启用了终点检测。

公开(公告)号：US07074317B2

公开(公告)日：2006-07-11

申请号：US10436427

申请日：2003-05-12

Applicant: Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

Inventor： Albert Birner ,  Dirk Schumann ,  Matthias Goldbach

IPC: H05K3/07

CPC classification number: H01L21/3063 ,  C25F3/12 ,  H01L27/10861 ,  H01L28/40

Abstract: An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 μm can be produced on p-doped silicon having a very low resistivity at a high etching rate.

Abstract translation: 提供电化学方法用于在p掺杂硅中制造用于大规模集成半导体存储器的非常高的直径/深度纵横比的沟槽电容器的沟槽。 可以以高蚀刻速率在具有非常低电阻率的p掺杂硅上产生直径小于约100nm且深度大于10um的沟槽（大孔）。

公开(公告)号：US20060134871A1

公开(公告)日：2006-06-22

申请号：US11017194

申请日：2004-12-20

Applicant: Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

Inventor： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC: H01L21/336

CPC classification number: H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

Abstract: Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

公开(公告)号：US20050173729A1

公开(公告)日：2005-08-11

申请号：US11035705

申请日：2005-01-14

Applicant: Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

Inventor： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/085 ,  H01L27/105 ,  H01L29/49 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC classification number: H01L29/4983 ,  H01L21/28247 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/6656

Abstract: The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).

Abstract translation: 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于 由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质 （5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60） 以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。