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    Method for producing a semiconductor structure
    1.
    发明申请
    Method for producing a semiconductor structure 审中-公开
    半导体结构的制造方法

    公开(公告)号：US20070111547A1

    公开(公告)日：2007-05-17

    申请号：US11582656

    申请日：2006-10-18

    Applicant: Thomas Hecht ,  Stefan Jakschik ,  Christian Kapteyn

    Inventor： Thomas Hecht ,  Stefan Jakschik ,  Christian Kapteyn

    IPC: H01L21/31

    CPC classification number: H01L21/31111 ,  H01L21/28202 ,  H01L21/823857 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/78

    Abstract: In a method for producing a semiconductor structure a substrate is provided, a dielectric layer comprising at least one metal oxide is formed on the substrate, and a nitrided layer is formed from the dielectric layer. The nitrided layer comprises either at least one metal nitride corresponding to the metal oxide or a metal oxynitride. The nitrided layer is removed selectively with respect to the dielectric layer in a predetermined etching medium.

    Abstract translation: 在制造半导体结构体的方法中，提供了基板，在基板上形成包含至少一种金属氧化物的电介质层，并且从电介质层形成氮化层。 氮化层包括至少一种对应于金属氧化物的金属氮化物或金属氮氧化物。 在预定的蚀刻介质中相对于电介质层选择性地去除氮化层。

    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells
    2.
    发明申请
    Stacked capacitor and method for producing stacked capacitors for dynamic memory cells 失效
    叠层电容器和用于制造用于动态存储单元的叠层电容器的方法

    公开(公告)号：US20070059893A1

    公开(公告)日：2007-03-15

    申请号：US11518504

    申请日：2006-09-07

    Applicant: Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    Inventor： Stephan Kudelka ,  Peter Moll ,  Stefan Jakschik ,  Odo Wunnicke

    IPC: H01L21/336

    CPC classification number: H01L28/90 ,  H01L27/10814 ,  H01L27/10852

    Abstract: A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.

    Abstract translation: 一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部 屏蔽层（40）的至少部分（42）连接到接触插塞（26）。 为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。 在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路 在相邻电极之间。

    Method for fabricating an electrical component
    4.
    发明申请
    Method for fabricating an electrical component 有权
    电气部件的制造方法

    公开(公告)号：US20060234463A1

    公开(公告)日：2006-10-19

    申请号：US11399811

    申请日：2006-04-07

    Applicant: Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    Inventor： Alejandro Avellan ,  Thomas Hecht ,  Stefan Jakschik ,  Uwe Schroeder

    IPC: H01L21/20 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

    CPC classification number: H01L28/65 ,  H01L27/1087 ,  H01L29/66181

    Abstract: An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric (130) and at least one connection electrode (120, 140) are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric (130) or the connection electrode (120, 140) are formed in such a manner that transient polarization effects are prevented or at least reduced.

    Abstract translation: 制造诸如DRAM半导体存储器或场效应晶体管的电气部件。 制造具有电介质（130）和至少一个连接电极（120,140）的至少一个电容器。 为了使得制造的电容器即使对于非常小的电容器结构也具有最佳的存储特性，电介质（130）或连接电极（120,140）形成为使得瞬态极化效应被防止或至少减小。

    Gate Electrode Structure, MOS Field Effect Transistors and Methods of Manufacturing the Same
    7.
    发明申请
    Gate Electrode Structure, MOS Field Effect Transistors and Methods of Manufacturing the Same 有权
    栅电极结构，MOS场效应晶体管及其制造方法

    公开(公告)号：US20080197428A1

    公开(公告)日：2008-08-21

    申请号：US11675460

    申请日：2007-02-15

    Applicant: Stefan Jakschik ,  Thomas Hecht

    Inventor： Stefan Jakschik ,  Thomas Hecht

    IPC: H01L29/78 ,  H01L21/4763

    CPC classification number: H01L21/28026 ,  H01L21/28061 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/7833 ,  H01L29/7845

    Abstract: A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.

    Abstract translation: 栅电极结构包括至少一个双层，其中每个双层包括镀膜和应力放大膜。 镀膜包括多晶材料。 应力放大器膜确定多晶材料的结晶结果，其中通过镀层诱导的机械应力被放大。 可能在结晶底物中诱导拉伸或压缩应变。 可以增加电子或空穴迁移率，并可提高MOS场效应晶体管的导通电阻特性。

    Method for fabricating microchips using metal oxide masks
    8.
    发明授权
    Method for fabricating microchips using metal oxide masks 有权
    使用金属氧化物掩模制造微芯片的方法

    公开(公告)号：US07268037B2

    公开(公告)日：2007-09-11

    申请号：US11040091

    申请日：2005-01-24

    Applicant: Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

    Inventor： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

    IPC: H01L21/8242

    CPC classification number: H01L27/1087 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31616 ,  H01L29/66181

    Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

    Abstract translation: 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

    Automatic layer deposition process
    9.
    发明申请
    Automatic layer deposition process 审中-公开
    自动层沉积工艺

    公开(公告)号：US20070161180A1

    公开(公告)日：2007-07-12

    申请号：US11331441

    申请日：2006-01-13

    Applicant: Elke Erben ,  Stefan Jakschik ,  Alfred Kersch ,  Angela Link ,  Jonas Sundqvist

    Inventor： Elke Erben ,  Stefan Jakschik ,  Alfred Kersch ,  Angela Link ,  Jonas Sundqvist

    IPC: H01L21/8242

    CPC classification number: C23C16/45531 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/3141 ,  H01L21/318 ,  H01L28/40

    Abstract: The atomic layer deposition process according to the invention provides the following steps for the production of homogeneous layers on a substrate. The substrate is introduced into a reaction chamber. A first precursor is introduced into the reaction chamber, which first precursor reacts on the surface of the substrate to form an intermediate product. A second precursor is introduced into the reaction chamber, which second precursor has a low sticking coefficient and reacts with part of the intermediate product to form a first product. A third precursor is introduced into the reaction chamber, which third precursor has a high sticking coefficient and reacts with the remaining part of the intermediate product to form a second product. The second precursor and its first product reduce the effective sticking coefficient of the third precursor by partially covering the surface.

    Abstract translation: 根据本发明的原子层沉积方法提供了在基底上生产均质层的以下步骤。 将基底引入反应室。 将第一前体引入反应室，其中第一前体在基材的表面上反应形成中间产物。 将第二前体引入反应室，该第二前体具有低粘附系数并与部分中间产物反应以形成第一产物。 将第三前体引入反应室，该第三前体具有高粘附系数并与中间产物的剩余部分反应以形成第二产物。 第二种前体及其第一种产物通过部分覆盖表面来降低第三种前体的有效粘附系数。

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