公开(公告)号：US06313622B1

公开(公告)日：2001-11-06

申请号：US09484227

申请日：2000-01-18

申请人： Takahiro Seki ,  Katsunori Seno

发明人： Takahiro Seki ,  Katsunori Seno

IPC分类号： G01R2500

CPC分类号： H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K19/00384 ,  H03K2005/00104 ,  H03L7/091 ,  H03L2207/00

摘要： A power source voltage controller which can set the optimal margin for a replica circuit and shorten the time for the power source voltage to converge to the optimal value, having a replica circuit for monitoring a delay time of a critical path by propagating a reference signal having a power source voltage-delay characteristic approximately equivalent to a critical path in a semiconductor circuit, a phase difference detection circuit and an encoder receiving a delay signal by the replica circuit and the reference signal and detecting the phase difference of the delay signal from the reference signal and outputting the detection result as phase difference information, voltage control circuits for generating a power source voltage of a value based on a phase difference information signal and supplying it to the semiconductor circuit and the replica circuit, and a delay error correction circuit arranged at the input side of the reference signal of the replica circuit and correcting the delay difference with the critical path.

摘要翻译： 一种电源电压控制器，其可以设置复制电路的最佳余量并缩短电源电压收敛到最佳值的时间，具有用于通过传播具有关键路径的延迟时间的参考信号来监视关键路径的延迟时间的复制电路， 大致相当于半导体电路中的关键路径的电源电压延迟特性，相位差检测电路和由复制电路接收延迟信号的编码器和参考信号，并检测来自参考的延迟信号的相位差 信号并输出​​检测结果作为相位差信息;电压控制电路，用于产生基于相位差信息信号的值的电源电压并将其提供给半导体电路和复制电路;以及延迟误差校正电路，布置在 复制电路的参考信号的输入侧并校正d 与关键路线的差距。

公开(公告)号：US5327382A

公开(公告)日：1994-07-05

申请号：US942627

申请日：1992-09-09

申请人： Katsunori Seno ,  Kurt Knorpp

发明人： Katsunori Seno ,  Kurt Knorpp

IPC分类号： G01R31/28 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/24

摘要： In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.

摘要翻译： 在具有用于正常存储器单元和冗余存储器单元的独立存储器区域的单芯片半导体存储器中，通过使冗余存储器区域响应，冗余单元以并行或多位测试模式与其所代替的正常单元同时测试 同时检测多位测试模式的状态，存在用于被测存储单元的编程冗余位和正常存储器矩阵的可操作选择。

公开(公告)号：US06295242B1

公开(公告)日：2001-09-25

申请号：US08722486

申请日：1996-09-27

申请人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

发明人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

IPC分类号： G11C1140

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor means and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

摘要翻译： 电流感测级联差分放大器具有特殊的偏置电路，其提供低阻抗输入和高阻抗输出，由此可以级联地连接多个级。 可选地，有源电流源用作数据线的上拉，以增加输出阻抗并提高数据线共模电平。 该放大器在大规模，快速接入半导体装置中作为电流感测读出放大器执行，并且在该应用中，存储器不需要均衡时钟信号，而且多个级联级的存取时间也不会实质上减慢。

公开(公告)号：US5757689A

公开(公告)日：1998-05-26

申请号：US565777

申请日：1995-12-01

申请人： Katsunori Seno

发明人： Katsunori Seno

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  G11C5/06 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C11/418 ,  G11C11/419 ,  G11C7/12

摘要： A semiconductor memory device including a plurality of memory cells arranged in a matrix; a plurality of bit lines; and a plurality of word lines controlled by column addresses for the same row addresses of the memory cells, wherein memory cells belonging to the same row are operatively connected to the bit lines by the plurality of word lines having the same row address and different column addresses.

摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的多个存储单元; 多个位线; 以及由存储器单元的相同行地址的列地址控制的多个字线，其中属于同一行的存储单元通过具有相同行地址和不同列地址的多个字线可操作地连接到位线 。

公开(公告)号：US5528187A

公开(公告)日：1996-06-18

申请号：US229787

申请日：1994-04-19

申请人： Hiroshi Sato ,  Katsunori Seno

发明人： Hiroshi Sato ,  Katsunori Seno

IPC分类号： G06F1/00 ,  G06F1/10 ,  G06F1/12 ,  G06F13/42 ,  H03K5/15 ,  H03L7/00 ,  H03L7/06 ,  H04L7/00 ,  H03K5/13

CPC分类号： G06F1/10 ,  H03K5/1508 ,  H04L7/0008

摘要： Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clock lines, and a center phase signal generating means generates a clock signal having a phase which is in the center of two clock signals of differing phase obtained from arbitrary points on the pair of clock lines which are at equal distances from the point at which the clock line is bent over. By using pairs of clock signals of differing phases taken at equal distances from the bend over point, three clock signals all having equal phase are obtained.

摘要翻译： 即使当在时钟线上发送的时钟信号中发生信号延迟时，也会形成相位相位的时钟信号。 在使用从公共时钟线获取的时钟信号同步电路元件的时钟同步电路中，时钟线在中间弯曲成一对时钟线，并且中心相位信号发生装置产生具有相位的时钟信号 从与时钟线弯曲的点相等距离的一对时钟线上的任意点获得的不同相位的两个时钟信号的中心。 通过使用在与弯曲点相等的距离处取得的不同相位的时钟信号对，获得全部具有相等相位的三个时钟信号。

公开(公告)号：US5384503A

公开(公告)日：1995-01-24

申请号：US942296

申请日：1992-09-09

申请人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

发明人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

IPC分类号： G11C11/419 ,  G11C7/10 ,  G11C11/409 ,  H03K5/22

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor memory and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

摘要翻译： 电流感测级联差分放大器具有特殊的偏置电路，其提供低阻抗输入和高阻抗输出，由此可以级联地连接多个级。 可选地，有源电流源用作数据线的上拉，以增加输出阻抗并提高数据线共模电平。 放大器在大规模，快速存取半导体存储器中作为电流感测读出放大器执行，并且在该应用中，存储器不需要均衡时钟信号，而且多个级联级的访问时间也不会实质上减慢。

公开(公告)号：US06414527B1

公开(公告)日：2002-07-02

申请号：US09484240

申请日：2000-01-18

申请人： Katsunori Seno ,  Takahiro Seki ,  Tetsuo Kondo

发明人： Katsunori Seno ,  Takahiro Seki ,  Tetsuo Kondo

IPC分类号： H03L706

CPC分类号： G06F1/3296 ,  G06F1/10 ,  G06F1/3203 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  Y02D10/172

摘要： A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an adjustable delay device for example between an output side of the replica circuit and a phase comparator, the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate with a margin from the critical path delay of the semiconductor circuit, whereby it becomes possible to prevent setting of an excessive margin and becomes possible to increase the margin when the margin ends up smaller than expected and therefore it becomes possible to flexibly and efficiently configure the replica circuit, and a method of constitution of the same.

摘要翻译： 一种半导体器件，其具有作为与半导体电路中选择为关键路径的路径配置的等效电路的复制电路，以及例如在复制电路的输出侧和相位比较器之间的可调延迟器件，延迟 延迟器件的值在芯片生产之后可调整到使得包括复制电路的复制系统能够从半导体电路的关键路径延迟可靠地运行的值，从而可以防止设置过大的余量 并且当边缘小于预期时可以增加余量，并且因此可以灵活且有效地配置复制电路及其结构的方法。

公开(公告)号：US5848015A

公开(公告)日：1998-12-08

申请号：US693997

申请日：1996-08-08

申请人： Katsunori Seno

发明人： Katsunori Seno

IPC分类号： G11C7/12 ,  G11C7/00

CPC分类号： G11C7/12

摘要： A precharge halt access mode system reduces the power consumed during sequential accesses of the memory cells within a memory block. During sequential accesses to the memory cells within a row of the memory block in a synchronous system, the bitlines within the memory are only precharged after the memory access to the last memory cell within the row is complete. After accesses to the other memory cells within the row, the precharging operation of the bitlines within the memory block is halted by a halt precharge logic circuit. Once the memory access to the last column within the memory block is detected the precharging of the bitlines is performed. During sequential accesses to the memory cells within a row in an asynchronous system, the bitlines within the memory block are only precharged during an access to the first memory cell within a row. A wordline disabling circuit will disable a wordline signal after an access to the first memory cell is complete. Each column includes a column gate which controls the accesses to each column and the activated memory cell. During a read operation, when a column gate is closed, the data on the bitlines of that column is coupled to inputs of a sense amplifier circuit. The sense amplifier circuit detects the sense of the data and generates an appropriate output. After each memory access operation to the memory block, the inputs to the sense amplifier are precharged. If a precharge halt access mode control signal is disabled the bitlines within a memory block are precharged after each memory access to the memory block.

摘要翻译： 预充电暂停访问模式系统减少了在存储器块内的存储器单元的顺序访问期间消耗的功率。 在对同步系统中的存储器块行内的存储器单元的顺序访问期间，只有存储器中的位线才能完成对该行中的最后一个存储器单元的存储器访问之后的预充电。 在访问行内的其他存储单元之后，存储器块内的位线的预充电操作由停止预充电逻辑电路停止。 一旦检测到存储器块内的最后一列的存储器访问，则执行位线的预充电。 在对异步系统中的行内的存储器单元的顺序访问期间，存储器块内的位线仅在访问行内的第一存储器单元时被预充电。 在完成对第一个存储单元的访问之后，字线禁用电路将禁用字线信号。 每列包括一个列门控制对每列和激活的存储单元的访问。 在读操作期间，当列门关闭时，该列的位线上的数据耦合到读出放大器电路的输入。 读出放大器电路检测数据的感觉并产生适当的输出。 在对存储器块的每个存储器访问操作之后，对读出放大器的输入进行预充电。 如果禁止预充电停止访问模式控制信号，则在存储器块的每个存储器访问之后，存储器块内的位线被预充电。

公开(公告)号：US06924679B2

公开(公告)日：2005-08-02

申请号：US09959997

申请日：2001-03-13

申请人： Katsunori Seno ,  Akihiko Hashiguchi ,  Tetsuo Kondo ,  Takahiro Seki

发明人： Katsunori Seno ,  Akihiko Hashiguchi ,  Tetsuo Kondo ,  Takahiro Seki

IPC分类号： G06F1/10 ,  G06F1/32 ,  H03K3/354 ,  H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  H03K5/14 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/06

CPC分类号： G06F1/324 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3296 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00026 ,  H03K2005/00078 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0996 ,  Y02D10/126 ,  Y02D10/172

摘要： A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit 11, an input signal generation circuit 12 able to change the phase difference i of a reference signal outφi and an input signal outφ0 in accordance with a control signal Si when generating the two signals from a clock, a monitor circuit 13 having a characteristic between a power supply voltage and delay the same as that of a critical path of the semiconductor circuit 11, propagating the input signal outφ0, and outputting a delayed signal outφ0′ to be delayed exactly by a time equivalent to a delay of the critical path (or smaller by a constant ratio), a delay detection circuit 14 for detecting a delay of the delayed signal outφ0′ relative to the reference signal outφi, and a power supply voltage control circuit 15 for controlling a power supply voltage VDD supplied to the semiconductor device 11 and the monitor circuit 13 based on the detection result.

摘要翻译： 一种电源电压控制装置，包括具有广泛用途的输入信号生成电路或新颖结构的小型监视电路，以及半导体电路及其驱动方法，具有半导体电路11，输入信号发生电路 12，当从时钟产生两个信号时，能够根据控制信号Si改变参考信号outphii的相位差i和输入信号outphi0，具有电源电压和延迟电源电压之间的特性的监视器电路13 与半导体电路11的关键路径相同，传播输入信号outphi 0，并输出延迟信号outphi 0'以精确地延迟等于关键路径的延迟的时间（或更小的一定比例 ），延迟检测电路14，用于检测延迟信号outphi 0'相对于参考信号outphii的延迟;以及电源电压控制电路15，用于 根据检测结果控制提供给半导体装置11和监视电路13的电源电压V DD。

公开(公告)号：US06222410B1

公开(公告)日：2001-04-24

申请号：US09342064

申请日：1999-06-29

申请人： Katsunori Seno

发明人： Katsunori Seno

IPC分类号： G06F104

CPC分类号： H03K19/00323 ,  H03K19/0013

摘要： A semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to a maximum, wherein delay paths to which low threshold voltage gate elements are applied are restricted to delay paths in a range from a maximum delay value before a lowering of a threshold voltage (at a higher speed than this) to a new maximum delay value in a case where low threshold voltage gate elements are applied to this (at a lower speed than this), whereby a leakage current due to low threshold voltage transistors can be kept to the minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to the maximum, thereby solving the problem of an unrequired leakage current applied to a chip over a wide range.

摘要翻译： 一种半导体电路，其能够在将阈值电压降低到最大的同时提高速度的效果的同时将漏电流保持为最小，其中施加低阈值电压门元件的延迟路径被限制为延迟路径 在将低阈值电压门元件施加到该阈值电压（以比此更高的速度）降低到新的最大延迟值之前的最大延迟值的范围内（以比此更低的速度） ，由此由于阈值电压降低到最大，由于低阈值电压晶体管的泄漏电流可以保持最小，同时提出了由于将阈值电压降至最大的速度提高的效果，从而解决了施加到 芯片范围很广。