公开(公告)号：US06295242B1

公开(公告)日：2001-09-25

申请号：US08722486

申请日：1996-09-27

申请人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

发明人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

IPC分类号： G11C1140

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor means and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

摘要翻译： 电流感测级联差分放大器具有特殊的偏置电路，其提供低阻抗输入和高阻抗输出，由此可以级联地连接多个级。 可选地，有源电流源用作数据线的上拉，以增加输出阻抗并提高数据线共模电平。 该放大器在大规模，快速接入半导体装置中作为电流感测读出放大器执行，并且在该应用中，存储器不需要均衡时钟信号，而且多个级联级的存取时间也不会实质上减慢。

公开(公告)号：US5384503A

公开(公告)日：1995-01-24

申请号：US942296

申请日：1992-09-09

申请人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

发明人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

IPC分类号： G11C11/419 ,  G11C7/10 ,  G11C11/409 ,  H03K5/22

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069

摘要： A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor memory and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

摘要翻译： 电流感测级联差分放大器具有特殊的偏置电路，其提供低阻抗输入和高阻抗输出，由此可以级联地连接多个级。 可选地，有源电流源用作数据线的上拉，以增加输出阻抗并提高数据线共模电平。 放大器在大规模，快速存取半导体存储器中作为电流感测读出放大器执行，并且在该应用中，存储器不需要均衡时钟信号，而且多个级联级的访问时间也不会实质上减慢。

公开(公告)号：US5519712A

公开(公告)日：1996-05-21

申请号：US323053

申请日：1994-10-12

申请人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

发明人： Lee-Lean Shu ,  Kurt Knorpp ,  Katsunori Seno

IPC分类号： G01R31/28 ,  G11C11/413 ,  G11C29/34 ,  G11C29/38 ,  G11C29/00

CPC分类号： G11C29/38

摘要： A test circuit for a single chip semiconductor memory array, located in the chip, enables testing of all columns along a word lines without additional column readout circuits. A pair of current detecting differential amplifiers are connected to the bit lines of multiple memory cells along a word line, and the amplifier outputs are compared to generate a pass/fail signal during a read access.

摘要翻译： 位于芯片中的单芯片半导体存储器阵列的测试电路使得能够沿着字线测试所有列，而不需要附加的列读出电路。 一对电流检测差分放大器沿着字线连接到多个存储器单元的位线，并且在读取访问期间比较放大器输出以产生通过/失败信号。

公开(公告)号：US5457407A

公开(公告)日：1995-10-10

申请号：US268118

申请日：1994-07-06

申请人： Lee-Lean Shu ,  Kurt Knorpp

发明人： Lee-Lean Shu ,  Kurt Knorpp

IPC分类号： H03H7/38 ,  H03K17/12 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/0005

摘要： An output buffer comprises a reference circuit having a plurality of reference transistors connected in parallel to each other and a output driver circuit having a corresponding plurality of driver transistors connected in parallel with each other. The reference transistors and the driver transistors both have varying widths with the widths of the reference transistors being a binary fraction, for instance one fourth, smaller than the widths of the corresponding output driver transistors. The transistors in the reference circuit are selectively conducted in order to match an impedance of the reference transistors to the impedance of a user selected resistor, representing a fraction of the impedance of a transmission line. The selection of the reference transistors also determines the selection of the driver transistors and consequently causes the impedance of the output driver to match the impedance of the transmission line. The reduction of the reference circuit by the binary fraction reduces the size of the overall circuit, lowers power consumption, and allows a matched layout between the transistors of the output driver and the reference circuit.

摘要翻译： 输出缓冲器包括具有彼此并联连接的多个参考晶体管的参考电路和具有彼此并联连接的相应多个驱动晶体管的输出驱动器电路。 参考晶体管和驱动器晶体管都具有变化的宽度，参考晶体管的宽度是二进制分数，例如比对应的输出驱动晶体管的宽度小四分之一。 参考电路中的晶体管被​​选择性地导通，以便将参考晶体管的阻抗与用户选择的电阻器的阻抗相匹配，代表传输线的阻抗的一部分。 参考晶体管的选择也决定了驱动晶体管的选择，从而使输出驱动器的阻抗匹配传输线的阻抗。 通过二进制分数的参考电路的减少减小了整个电路的尺寸，降低了功耗，并且允许输出驱动器和参考电路的晶体管之间的匹配布局。

公开(公告)号：US06775193B1

公开(公告)日：2004-08-10

申请号：US10405265

申请日：2003-04-01

申请人： Taiching Shyu ,  Lee-Lean Shu

发明人： Taiching Shyu ,  Lee-Lean Shu

IPC分类号： G11C700

CPC分类号： G11C29/40 ,  G11C29/26 ,  G11C2029/0401 ,  G11C2029/2602

摘要： The present invention provides a system and method for testing embedded memories. The present invention logically combines many different embedded memories into one or more large, virtual memory blocks in order to test multiple memories together. The invention defines the X and/or Y address space in all memories in order to cover all memories combined. Compare circuits associated with each memory module are used to compare the data output from each memory cell to an expected value (e.g., to a value that would be expected if the memory cell was operating properly). The invention further uses mask logic to “mask out” any unimplemented address space in each individual memory. The mask logic will always indicate that the comparison or memory test passed when unimplemented addresses are selected. The results of the comparison may be bundled and multiplexed to a test input/output port.

摘要翻译： 本发明提供了一种用于测试嵌入式存储器的系统和方法。 本发明将许多不同的嵌入式存储器逻辑地组合成一个或多个大的虚拟存储器块，以便一起测试多个存储器。 本发明定义了所有存储器中的X和/或Y地址空间，以覆盖所有组合的存储器。 与每个存储器模块相关联的比较电路用于将来自每个存储器单元的数据输出与预期值进行比较（例如，如果存储器单元正常运行则将预期的值）。 本发明还使用掩码逻辑来“屏蔽”每个单独存储器中的任何未实现的地址空间。 当选择未实现的地址时，掩码逻辑将始终指示比较或内存测试通过。 比较结果可以捆绑并复用到测试输入/输出端口。

公开(公告)号：US5355343A

公开(公告)日：1994-10-11

申请号：US949217

申请日：1992-09-23

申请人： Lee-Lean Shu ,  Chenming W. Tung

发明人： Lee-Lean Shu ,  Chenming W. Tung

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A static memory array incorporates a bit line equalization transistor which is normally conductive so that the quiescent condition of the bit lines is to remain equalized. The equalization transistor is cut off for a predetermined period in response to detection of address transition. When a subsequent address transition occurs before the expiration of a predetermined period, the equalization transistor conducts again briefly, which conduction is followed by a period of nonconduction, for a predetermined duration, as long as another address transition is not detected. The equalization technique is applicable to local data lines as well as the bit lines of the memory.

摘要翻译： 静态存储器阵列包含正常导通的位线均衡晶体管，使得位线的静态条件保持均衡。 响应于地址转换的检测，均衡晶体管被切断预定的周期。 当在预定周期期满之前发生随后的地址转换时，只要没有检测到另一个地址转换，均衡晶体管再次短暂地导通，该导通之后是非导通的周期，持续预定的持续时间。 均衡技术适用于本地数据线以及存储器的位线。

公开(公告)号：US07292490B1

公开(公告)日：2007-11-06

申请号：US11223194

申请日：2005-09-08

申请人： Lee-Lean Shu ,  Stephen Lee

发明人： Lee-Lean Shu ,  Stephen Lee

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40611

摘要： The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.

摘要翻译： 本发明提供了一种用于刷新DRAM器件而不中断或禁止DRAM器件的读和写操作的系统和方法。 系统可以包括选择性地产生执行刷新操作的请求的刷新控制电路和耦合到刷新控制电路的刷新地址计数器，并且响应于接收到刷新请求而产生刷新地址。 刷新地址对应于要刷新的DRAM阵列的字线。 地址控制和切换电路可以耦合到刷新控制电路。 地址控制和切换电路选择性地将读/写地址和刷新地址发送到DRAM阵列，以便对DRAM阵列执行刷新操作，而不会妨碍读和写操作。

公开(公告)号：US06762973B2

公开(公告)日：2004-07-13

申请号：US10322215

申请日：2002-12-17

申请人： Lee-Lean Shu ,  Chenming W. Tung ,  Stephen Lee

发明人： Lee-Lean Shu ,  Chenming W. Tung ,  Stephen Lee

IPC分类号： G11C1300

CPC分类号： G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the. SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.

摘要翻译： 本发明为SRAM器件提供数据相干逻辑。 本发明利用数据选通信号和输出选通信号来控制写入和读出的数据。 来自输入/输出板的SRAM器件。 数据相干逻辑被设计为解决数据和输出选通信号之间的时序冲突。 当在写入操作之后紧接着的读取操作中请求的数据发生匹配时，逻辑选择性地延迟输出选通信号。 该延迟允许在从设备输出之前注册和选择数据的足够的时间。

公开(公告)号：US08638144B1

公开(公告)日：2014-01-28

申请号：US12982839

申请日：2010-12-30

申请人： Jyn-Bang Shyu ,  Yoshinori Sato ,  Jae Hyeong Kim ,  Lee-Lean Shu

发明人： Jyn-Bang Shyu ,  Yoshinori Sato ,  Jae Hyeong Kim ,  Lee-Lean Shu

IPC分类号： H03L7/06

CPC分类号： H03L7/095 ,  H03L7/0814 ,  H03L7/0816

摘要： Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.

摘要翻译： 公开了与控制时钟信号相关联的系统和方法。 在一个示例性实现中，提供了延迟锁定环（DLL）和/或延迟/相位检测电路。 此外，这种电路可以包括数字相位检测电路，数字延迟控制电路，模拟相位检测电路和模拟延迟控制电路。 实现可以包括由于抖动或噪声而防止转换回解锁状态的配置。

公开(公告)号：US08400200B1

公开(公告)日：2013-03-19

申请号：US13179520

申请日：2011-07-09

申请人： Jae Hyeong Kim ,  Jyn-Bang Shyu ,  Lee-Lean Shu

发明人： Jae Hyeong Kim ,  Jyn-Bang Shyu ,  Lee-Lean Shu

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.