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    MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICE 审中-公开
    内存设备

    公开(公告)号：US20160343715A1

    公开(公告)日：2016-11-24

    申请号：US14720831

    申请日：2015-05-24

    Applicant: Inotera Memories, Inc.

    Inventor： Tieh-Chiang WU

    IPC: H01L27/108 ,  H01L29/06

    CPC classification number: H01L29/0642 ,  H01L27/10823 ,  H01L27/10888

    Abstract: A memory device including a substrate, a gate structure, a first active region, a second active region, and a contact. The gate structure is disposed in the substrate. The first active region and the second active region are disposed in the substrate and are respectively disposed at opposite sides of the gate structure. The gate structure, the first active region, and the second active region form a memory cell. The contact is disposed on and attached to the first active region. An interface between the contact and the first active region is saddle-shaped.

    Abstract translation: 一种存储器件，包括衬底，栅极结构，第一有源区，第二有源区和接触。 栅极结构设置在基板中。 第一有源区和第二有源区设置在衬底中，并且分别设置在栅极结构的相对侧。 栅极结构，第一有源区和第二有源区形成存储单元。 触点设置在第一活动区域上并附接到第一活动区域。 触点与第一有源区之间的界面是鞍形的。

    Semiconductor device and fabrication method therefor
    8.
    发明授权
    Semiconductor device and fabrication method therefor 有权
    半导体器件及其制造方法

    公开(公告)号：US09496358B2

    公开(公告)日：2016-11-15

    申请号：US14289936

    申请日：2014-05-29

    Applicant: INOTERA MEMORIES, INC.

    Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Heng Hao Hsu ,  Yu Jing Chang ,  Hsu Chiang

    IPC: H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/4236 ,  H01L21/26586 ,  H01L29/66621 ,  H01L29/7834

    Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

    Abstract translation: 半导体电子器件结构包括其中设置有沟槽的衬底，设置在沟槽中的栅电极和设置在沟槽中的表面上的栅极电介质层。 基板和栅电极通过栅介质层彼此电绝缘。 衬底还具有一对掺杂区域。 掺杂区域各自沿沟槽的两个相应横向侧面垂直设置。 掺杂区域各自具有布置在第一部分顶部的第一部分和第二部分。 第一部分垂直延伸到与栅电极对准的衬底部分。 第一部分的横向尺寸小于第二部分的横向尺寸，并且第一部分的掺杂浓度比第二部分的掺杂浓度轻。

    Split contact structure and fabrication method thereof
    9.
    发明授权
    Split contact structure and fabrication method thereof 有权
    分离接触结构及其制造方法

    公开(公告)号：US09401326B1

    公开(公告)日：2016-07-26

    申请号：US14720830

    申请日：2015-05-24

    Applicant: INOTERA MEMORIES, INC.

    Inventor： Cheng-Yeh Hsu ,  Hsin-Pin Huang ,  Chih-Hao Cheng

    IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108

    CPC classification number: H01L27/10844 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10882

    Abstract: A split contact structure includes a semiconductor substrate having a major surface; a first upwardly protruding structure disposed on the major surface; a first cell contact region in the major surface and being close to the first upwardly protruding structure; a second upwardly protruding structure disposed on the major surface; a second cell contact region in the major surface and being close to the second upwardly protruding structure; a first patterned layer stacked on the first upwardly protruding structure; a second patterned layer stacked on the first upwardly protruding structure; a first contact structure disposed on a sidewall of the first upwardly protruding structure and being in direct contact with the first cell contact region; and a second contact structure disposed on a sidewall of the second upwardly protruding structure and being in direct contact with the second cell contact region.

    Abstract translation: 分割接触结构包括具有主表面的半导体衬底; 设置在主表面上的第一向上突出的结构; 主表面中的第一细胞接触区域并且靠近第一向上突出结构; 设置在主表面上的第二向上突出的结构; 在主表面中的第二细胞接触区域并且靠近第二向上突出的结构; 堆叠在第一向上突出结构上的第一图案层; 堆叠在第一向上突出结构上的第二图案层; 第一接触结构，其设置在所述第一向上突出结构的侧壁上并与所述第一电池接触区域直接接触; 以及第二接触结构，其设置在所述第二向上突出结构的侧壁上并与所述第二电池接触区域直接接触。

    METHOD OF FABRICATING SOURCE/DRAIN REGION AND SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN REGION FABRICATED BY THE SAME
    10.
    发明申请
    METHOD OF FABRICATING SOURCE/DRAIN REGION AND SEMICONDUCTOR STRUCTURE HAVING SOURCE/DRAIN REGION FABRICATED BY THE SAME 审中-公开
    制造源/排水区的方法及其制造的源/排水区的半导体结构

    公开(公告)号：US20160133711A1

    公开(公告)日：2016-05-12

    申请号：US14534882

    申请日：2014-11-06

    Applicant: INOTERA MEMORIES, INC.

    Inventor： YU NA CHOU ,  CHEN-KANG WEI ,  YI WEI CHUANG ,  RONG ZHEN CHEN ,  CHUN WEI YO

    IPC: H01L29/36 ,  H01L29/43 ,  H01L29/417 ,  H01L21/265 ,  H01L21/324

    CPC classification number: H01L21/26513 ,  H01L21/2236 ,  H01L21/2253 ,  H01L29/0847 ,  H01L29/66575

    Abstract: A method of fabricating source/drain region in a substrate includes the steps of: introducing an ion beam-line of a first material to a surface of the substrate at a first energy and a first dosage to implant the substrate with dopants of a first conductive type; and subsequently, introducing a plasma of a second material to the surface. The ion beam-line is introduced, at a second energy and a second dosage to implant the substrate with dopants of the first conductive type. The second dosage is greater than the first dosage and the implant depth of the plasma is less than the implant depth of the ion beam-line.

    Abstract translation: 在衬底中制造源极/漏极区域的方法包括以下步骤：将第一材料的离子束线以第一能量和第一剂量引入到衬底的表面，以用第一导电的掺杂剂注入衬底 类型; 并且随后将第二材料的等离子体引入到表面。 以第二能量和第二剂量引入离子束线，以用第一导电类型的掺杂剂注入衬底。 第二剂量大于第一剂量，并且等离子体的植入深度小于离子束线的植入深度。

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