公开(公告)号：US09496358B2

公开(公告)日：2016-11-15

申请号：US14289936

申请日：2014-05-29

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Neng-Tai Shih ,  Heng Hao Hsu ,  Yu Jing Chang ,  Hsu Chiang

IPC: H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/26586 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Abstract translation: 半导体电子器件结构包括其中设置有沟槽的衬底，设置在沟槽中的栅电极和设置在沟槽中的表面上的栅极电介质层。 基板和栅电极通过栅介质层彼此电绝缘。 衬底还具有一对掺杂区域。 掺杂区域各自沿沟槽的两个相应横向侧面垂直设置。 掺杂区域各自具有布置在第一部分顶部的第一部分和第二部分。 第一部分垂直延伸到与栅电极对准的衬底部分。 第一部分的横向尺寸小于第二部分的横向尺寸，并且第一部分的掺杂浓度比第二部分的掺杂浓度轻。

公开(公告)号：US20150243597A1

公开(公告)日：2015-08-27

申请号：US14190025

申请日：2014-02-25

Applicant: INOTERA MEMORIES, INC.

Inventor： Hsu Chiang ,  Yaw-Wen Hu

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498 ,  B81B7/00

CPC classification number: H01L23/291 ,  H01L23/3171 ,  H01L23/522 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate having a front side and a rear side, a plurality of dielectric layers on the front side, a plurality of interconnection circuit structures in the dielectric layers, and at least one backside passivation layer on the rear side. The backside passivation layer and the top passivation layer are made of the same material and have substantially the same thickness.

Abstract translation: 半导体器件包括具有前侧和后侧的衬底，前侧上的多个电介质层，电介质层中的多个互连电路结构以及后侧的至少一个后侧钝化层。 背面钝化层和顶部钝化层由相同的材料制成并具有基本上相同的厚度。

公开(公告)号：US08828843B2

公开(公告)日：2014-09-09

申请号：US13875442

申请日：2013-05-02

Applicant: Inotera Memories, Inc.

Inventor： Yaw-Wen Hu ,  Jung-Chang Hsieh ,  Kuen-Shin Huang ,  Jian-Wei Chen ,  Ming-Tai Chien

IPC: H01L21/4763 ,  H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/306

Abstract: A method of manufacturing an isolation structure includes forming a laminate structure on a substrate. A plurality trenches is formed in the laminate structure. Subsequently a pre-processing is effected to form a hydrophilic thin film having oxygen ions on the inner wall of the trenches. Spin-on-dielectric (SOD) materials are filled into the trenches. The hydrophilic think film having oxygen ions changes the surface tension of the inner wall of the trenches and increases SOD material fluidity.

Abstract translation: 隔离结构的制造方法包括在基板上形成层叠结构。 在层叠结构中形成多个沟槽。 随后进行预处理以在沟槽的内壁上形成具有氧离子的亲水性薄膜。 旋转电介质（SOD）材料被填充到沟槽中。 具有氧离子的亲水认知膜改变了沟槽内壁的表面张力，提高了SOD材料的流动性。

公开(公告)号：US20140117442A1

公开(公告)日：2014-05-01

申请号：US13831879

申请日：2013-03-15

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Hsu Chiang ,  Sheng-Hsiung Wu

IPC: H01L21/768 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Abstract translation: 半导体结构包括多个掩埋栅极，其设置在衬底中并具有第一源极和第二源极，覆盖多个掩埋栅极和衬底的层间电介质层以及包括第一插塞的核心双镶嵌插头，第二插塞 插头和绝缘槽。 绝缘槽设置在第一插头和第二插头之间，使得第一插头和第二插头相互电绝缘。 第一插头和第二插头分别穿透层间电介质层并且分别电连接到第一源极和第二源极。

公开(公告)号：US09184166B2

公开(公告)日：2015-11-10

申请号：US14272804

申请日：2014-05-08

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Vishnu Kumar Agarwal

IPC: H01L23/48 ,  H01L27/108 ,  H01L21/8242 ,  H01L21/331

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L28/90

Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.

Abstract translation: 本公开涉及包括半导体衬底，至少一个图案化加强层，多个下电极和支撑层的半导体器件。 至少一个图案化加强层布置在半导体衬底之上，其中至少一个图案化加强层具有多个加强结构，其构造成限定多个对准孔。 下电极布置在半导体衬底上，其中N个下电极通过每个对准孔，其中N是大于或等于1的整数。支撑层布置在至少一个图案化加强层的上方， 在下电极之间。

公开(公告)号：US09035366B2

公开(公告)日：2015-05-19

申请号：US14025087

申请日：2013-09-12

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Hung Chang Liao ,  Chung-Yuan Lee ,  Hsu Chiang ,  Sheng-Hsiung Wu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66477

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract translation: 半导体电子器件结构包括设置在衬底中的有源区阵列，隔离结构，多个凹入栅结构，多个字线和多个位线。 有源区域阵列具有多个活动区域列和多个有效区域行，其限定有源区域的阵列。 基板在其中央部形成有两个凹部。 每个凹入的栅极结构分别设置在凹部中。 在每个凹部中的基板上形成突出结构。 隔离结构的STI结构被布置在每对相邻的有效区域行之间。 字线设置在基板中，每个电路连接其下的栅极结构。 位线设置在有效区域之上，形成与字线的交叉图案。

公开(公告)号：US20140308807A1

公开(公告)日：2014-10-16

申请号：US14249357

申请日：2014-04-10

Applicant: INOTERA MEMORIES, INC.

Inventor： Yaw-Wen Hu ,  Ron Fu Chu ,  Tzung-Han Lee

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/3105 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/4236 ,  H01L29/4925 ,  H01L29/66621

Abstract: A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.

Abstract translation: 一种制造半导体存储器的方法包括以下步骤。 活性区域定义在底物中。 然后在活性区域上形成氧化物层。 对氧化物层进行表面处理。 沉积第一多晶硅层，缓冲层和硬掩模。 嵌入式存取器件形成在衬底的阵列区域中。 在形成凹入的访问设备之后，去除硬掩模和缓冲层，从而在周边区域中形成晶体管。 第二多晶硅层沉积在第一多晶硅层上。 然后将第一和第二多晶硅层蚀刻成栅极结构。

公开(公告)号：US09230967B2

公开(公告)日：2016-01-05

申请号：US14251765

申请日：2014-04-14

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu

IPC: H01L27/108 ,  H01L21/762

CPC classification number: H01L27/10805 ,  H01L21/76224 ,  H01L27/10885 ,  H01L29/0649

Abstract: The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.

Abstract translation: 本公开涉及在半导体衬底中形成自对准隔离沟槽的方法，包括以下步骤。 第一步是提供在其上限定多个活性区域的半导体衬底。 下一步是在每个有源区中形成至少两个掩埋位线，以及设置在至少两个掩埋位线上方和相对的绝缘结构。 下一步是在每个绝缘结构的侧壁上形成自对准间隔物。 最后一步是用自对准间隔物作为掩模选择性地去除半导体衬底以形成多个隔离沟槽。

公开(公告)号：US09070782B2

公开(公告)日：2015-06-30

申请号：US13831879

申请日：2013-03-15

Applicant: INOTERA MEMORIES, INC.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu ,  Hung-Chang Liao ,  Chung-Yuan Lee ,  Hsu Chiang ,  Sheng-Hsiung Wu

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/485 ,  H01L27/108

CPC classification number: H01L21/823456 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.

Abstract translation: 半导体结构包括多个掩埋栅极，其设置在衬底中并具有第一源极和第二源极，覆盖多个掩埋栅极和衬底的层间电介质层以及包括第一插塞的核心双镶嵌插头，第二插塞 插头和绝缘槽。 绝缘槽设置在第一插头和第二插头之间，使得第一插头和第二插头相互电绝缘。 第一插头和第二插头分别穿透层间电介质层并且分别电连接到第一源极和第二源极。

公开(公告)号：US09018733B1

公开(公告)日：2015-04-28

申请号：US14201932

申请日：2014-03-10

Applicant: Inotera Memories, Inc.

Inventor： Tzung-Han Lee ,  Yaw-Wen Hu

IPC: H01L21/02 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L27/1085 ,  H01L28/90

Abstract: A semiconductor structure includes a substrate having thereon at least one conductive region; a plurality of cylinder-shaped electrodes disposed on the substrate, wherein each of the cylinder-shaped electrodes has a horizontal portion that is in direct contact with the at least one conductive region and a vertical sidewall portion connecting the horizontal portion; an upper support structure comprising a first lattice structure that is situated in a first horizontal level that is lower than a tip portion of each of the cylinder-shaped electrodes; and a lower support structure comprising a second lattice structure that interlocks middle portions of the cylinder-shaped electrodes.

Abstract translation: 半导体结构包括其上具有至少一个导电区域的基板; 设置在基板上的多个圆柱形电极，其中每个圆柱形电极具有与至少一个导电区域直接接触的水平部分和连接水平部分的垂直侧壁部分; 上部支撑结构，其包括位于比每个所述圆柱形电极的尖端部分低的第一水平高度的第一格子结构; 以及下部支撑结构，其包括使所述圆柱形电极的中间部分互锁的第二格子结构。