公开(公告)号：US09693455B1

公开(公告)日：2017-06-27

申请号：US14227346

申请日：2014-03-27

Applicant: Seong Won Park ,  Hun Teak Lee ,  WoonJae Beak ,  MinJung Kim ,  ChangHwan Kim ,  ByungHyun Kwak ,  GwangTae Kim ,  HeeSoo Lee

Inventor： Seong Won Park ,  Hun Teak Lee ,  WoonJae Beak ,  MinJung Kim ,  ChangHwan Kim ,  ByungHyun Kwak ,  GwangTae Kim ,  HeeSoo Lee

IPC: H05K1/11 ,  H05K3/36 ,  H05K3/40 ,  H05K1/09 ,  H05K1/18 ,  H05K1/14 ,  H05K3/32 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/09 ,  H05K1/113 ,  H05K1/14 ,  H05K1/18 ,  H05K1/186 ,  H05K3/32 ,  H05K3/36 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/04 ,  H05K2203/061 ,  H05K2203/0733

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a copper film; a first metal layer directly on the copper film; an insulation layer directly on and over the first metal layer, the insulation layer having a via hole through the insulation layer; a conductive via within the via hole and directly on the first metal layer; a second metal layer directly on the conductive via and the insulation layer; a copper post directly on the copper film; a solder pad over the copper post; and an interposer coupled to the copper post and the solder pad.

公开(公告)号：US20110266700A1

公开(公告)日：2011-11-03

申请号：US13178331

申请日：2011-07-07

Applicant: Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

Inventor： Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2924/2065 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.

Abstract translation: 半导体封装的制造方法包括：提供衬底; 将半导体管芯安装在基板上，半导体管芯具有管芯焊盘; 将引线安装在基板上; 在所述引导指的侧面附接支撑基座; 并且在芯片焊盘和支撑基座之间附接电线互连，电线互连在芯片焊盘上具有球接合，并且在支撑基座上具有针脚接合。

公开(公告)号：US07759783B2

公开(公告)日：2010-07-20

申请号：US11608123

申请日：2006-12-07

Applicant: Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538 ,  H01L23/02 ,  H01L23/495 ,  H01L23/522 ,  H01L23/52 ,  H01L25/065 ,  H01L23/28 ,  H01L23/31 ,  H05K7/00

CPC classification number: H01L25/03 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; stacking a second device over a first device between the first lead-finger system and the second lead-finger system; connecting the second device to the second lead-finger system with a bump bond; stacking a dummy device over the second device; and connecting the first device to the first lead-finger system with a wire bond.

Abstract translation: 一种集成电路封装系统，包括：提供包括第一引线指系统和第二引线指系统的电互连系统; 在第一引线指系统和第二引指系统之间的第一器件上堆叠第二器件; 将所述第二装置连接到具有凸块接合的所述第二引线指系统; 在第二设备上堆叠虚拟设备; 以及用引线键将所述第一装置连接到所述第一引线指系统。

公开(公告)号：US07731078B2

公开(公告)日：2010-06-08

申请号：US11162617

申请日：2005-09-16

Applicant: Hun Teak Lee ,  Jong Kook Kim ,  ChulSik Kim ,  Ki Youn Jang

Inventor： Hun Teak Lee ,  Jong Kook Kim ,  ChulSik Kim ,  Ki Youn Jang

IPC: B23K31/00 ,  H01L23/48

CPC classification number: H01L24/85 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49175 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package system includes providing a die having a plurality of contact pads. A leadframe is formed having a plurality of lead fingers with the plurality of lead fingers having a fine pitch and each having a substantially trapezoidal cross-section. A plurality of bumps is formed on the plurality of lead fingers, the plurality of bumps are on the tops and extend down the sides of the plurality of lead fingers. A plurality of bond wires is attached to the plurality of contact pads and to the plurality of bumps. An encapsulant is formed over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.

Abstract translation: 半导体封装系统包括提供具有多个接触焊盘的管芯。 引导框架形成为具有多个引线指，多个引线指具有细间距，并且每个具有大致梯形的横截面。 多个凸点形成在多个引线指状物上，多个凸块位于顶部并且沿着多个引线指的侧面延伸。 多个接合线附接到多个接触焊盘和多个凸起。 在多个引线指，芯片和多个接合线之间形成密封剂，所述密封剂露出多个引线指的下表面。

公开(公告)号：US07407080B2

公开(公告)日：2008-08-05

申请号：US10971202

申请日：2004-10-22

Applicant: Kenny Lee ,  Hun-Teak Lee ,  Jong Kook Kim ,  Chulsik Kim ,  Ki-Youn Jang

Inventor： Kenny Lee ,  Hun-Teak Lee ,  Jong Kook Kim ,  Chulsik Kim ,  Ki-Youn Jang

IPC: B23K37/00

CPC classification number: B23K20/005 ,  B23K20/007 ,  B23K2101/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48451 ,  H01L2224/78302 ,  H01L2224/78901 ,  H01L2224/85205 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A capillary tip for a wire bonding tool has a chamfer provided with at least one annular groove. The annular groove is generally oriented in a plane perpendicular to the axis of the capillary. In a sectional view through the capillary axis, the groove profile may be generally part-oval or part circular, such as semicircular or half-oval; or generally rectangular; or generally triangular. In some embodiments the width of the groove profile at the face of the chamfer is at least about one-tenth, more usually at least about one-fifth, the length of the chamfer face; and less than about one-half, more usually less than about one-third, the length of the chamfer face. In some embodiments two or more such grooves are provided. The grooved chamfer can improve the transmission of ultrasonic energy to the wire ball during formation of the bond.

Abstract translation: 用于引线接合工具的毛细管尖端具有设置有至少一个环形槽的倒角。 环形槽通常在垂直于毛细管轴线的平面内定向。 在通过毛细管轴线的剖视图中，凹槽轮廓可以是大致为椭圆形或部分圆形的，例如半圆形或半椭圆形; 或大致矩形; 或一般为三角形。 在一些实施例中，在倒角的表面处的凹槽轮廓的宽度是倒角面的长度的至少约十分之一，更通常至少约五分之一; 并且小于倒角面的长度的大约一半，更通常小于约三分之一。 在一些实施例中，提供了两个或更多个这样的凹槽。 沟槽倒角可以在形成接合时改善超声能量传递到丝球。

公开(公告)号：US20080136005A1

公开(公告)日：2008-06-12

申请号：US11608826

申请日：2006-12-09

Applicant: Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。

公开(公告)号：US20060113665A1

公开(公告)日：2006-06-01

申请号：US11273635

申请日：2005-11-14

Applicant: Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra Pendse

Inventor： Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra Pendse

IPC: H01L23/48

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2924/2065 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. Also, such a package in which the package substrate includes a two-tier substrate, each tier including a plurality of lead fingers having a lead finger bond pitch about twice the die pad pitch, the lead fingers of the first tier and the second tier having a staggered arrangement. In some embodiments the support pedestal is formed using a wire bonding tool as in formation of a stud bump, and in such embodiments the support pedestal is metallurgically bonded to the lead finger. Also, a method for forming a wire bond interconnection between a semiconductor die and a substrate, by providing a die affixed on a die mount portion of a first side of a substrate and oriented with the active side oriented away from the substrate, the substrate having patterned traces including lead fingers in the first surface of the substrate; forming a support pedestal on a bond site of a lead finger; forming a first bond on a die pad; and forming a second bond on the support pedestal.

Abstract translation: 芯片焊盘和键合指状物之间的引线键合互连包括在引线指的键合位置处的支撑基座，芯片焊盘上的球接合以及支撑基座上的线圈接合，其中引线指 在焊接点处小于支撑基座的直径。 此外，包括安装在多个引线键合并且电连接到基板的裸片的半导体封装，其中每个引线键合包括接合到模具上的焊盘的线球，并且在与基板上的支撑基座上接合 引线指的键位置，并且其中引线指在键合位置处的宽度小于支撑基座的直径。 另外，封装基板包括双层基板的这种封装，每层包括多个引线指，其具有大约两倍于管芯焊盘间距的引线接合间距，第一层和第二层的引线指具有 交错排列 在一些实施例中，在形成柱形凸块时使用引线接合工具形成支撑基座，并且在这种实施例中，支撑基座冶金地结合到引线指。 另外，在半导体管芯和基板之间形成引线接合互连的方法，其特征在于，通过在基板的第一面的芯片安装部上设置模具，并且将所述有源面取向为远离所述基板，所述基板具有 图案化痕迹，包括在所述衬底的第一表面中的引线指; 在引线指的接合部位上形成支撑基座; 在芯片焊盘上形成第一键; 以及在所述支撑座上形成第二接合。

公开(公告)号：US20050218188A1

公开(公告)日：2005-10-06

申请号：US10971202

申请日：2004-10-22

Applicant: Kenny Lee ,  Hun-Teak Lee ,  Jong Kim ,  Chulsik Kim ,  Ki-Youn Jang

Inventor： Kenny Lee ,  Hun-Teak Lee ,  Jong Kim ,  Chulsik Kim ,  Ki-Youn Jang

IPC: B23K20/00 ,  B23K37/00 ,  H01L21/60 ,  H01L21/607

CPC classification number: B23K20/005 ,  B23K20/007 ,  B23K2101/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48451 ,  H01L2224/78302 ,  H01L2224/78901 ,  H01L2224/85205 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01204 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/20752 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A capillary tip for a wire bonding tool has a chamfer provided with at least one annular groove. The annular groove is generally oriented in a plane perpendicular to the axis of the capillary. In a sectional view thru the capillary axis, the groove profile may be generally part-oval or part circular, such as semicircular or half-oval; or generally rectangular; or generally triangular. In some embodiments the width of the groove profile at the face of the chamfer is at least about one-tenth, more usually at least about one-fifth, the length of the chamfer face; and less than about one-half, more usually less than about one-third, the length of the chamfer face. In some embodiments two or more such grooves are provided. The grooved chamfer can improve the transmission of ultrasonic energy to the wire ball during formation of the bond.

Abstract translation: 用于引线接合工具的毛细管尖端具有设置有至少一个环形槽的倒角。 环形槽通常在垂直于毛细管轴线的平面内定向。 在通过毛细管轴线的截面图中，凹槽轮廓可以是大致椭圆形或部分圆形，例如半圆形或半椭圆形; 或大致矩形; 或一般为三角形。 在一些实施例中，在倒角的表面处的凹槽轮廓的宽度是倒角面的长度的至少约十分之一，更通常地至少约五分之一; 并且小于倒角面的长度的大约一半，更通常小于约三分之一。 在一些实施例中，提供了两个或更多个这样的凹槽。 沟槽倒角可以在形成接合时改善超声能量传递到丝球。

公开(公告)号：US20130249117A1

公开(公告)日：2013-09-26

申请号：US13426529

申请日：2012-03-21

Applicant: Hun Teak Lee ,  DaeWook Yang ,  Yeongbeom Ko

Inventor： Hun Teak Lee ,  DaeWook Yang ,  Yeongbeom Ko

IPC: H01L23/498 ,  H01L21/98

CPC classification number: H01L21/563 ,  H01L21/6836 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/2731 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83871 ,  H01L2224/8388 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.

Abstract translation: 一种集成电路封装系统的制造方法，包括：提供具有与无效部分相对的有源侧的电路基板; 将非导电盖附接到活动侧; 形成将非导电盖和电路基板部分地切割成切口深度的分离间隙; 将背磨带附接到非导电盖; 去除所述非活性部分的一部分; 并通过去除背磨带露出非导电盖。

公开(公告)号：US20130032954A1

公开(公告)日：2013-02-07

申请号：US13649834

申请日：2012-10-11

Applicant: Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

Inventor： Hun Teak Lee ,  Tae Keun Lee ,  Soo Jung Park

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/31 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/315 ,  H01L24/48 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48227 ,  H01L2224/48479 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/48471 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成第一外部互连; 在第一外部互连下方安装第一集成电路管芯; 在第一集成电路管芯上以不在第一外部互连上的偏移配置堆叠第二集成电路管芯; 将所述第一集成电路管芯与所述第一外部互连件连接; 并且将所述第二集成电路管芯与所述第一外部互连件封装，并且所述第一集成电路管芯部分地露出。