公开(公告)号：US08256660B2

公开(公告)日：2012-09-04

申请号：US13053141

申请日：2011-03-21

Applicant: Hun Teak Lee ,  Jong Kook Kim ,  ChulSik Kim ,  Ki Youn Jang

Inventor： Hun Teak Lee ,  Jong Kook Kim ,  ChulSik Kim ,  Ki Youn Jang

IPC: B23K31/00 ,  H01L23/48

CPC classification number: H01L24/85 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49175 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.

Abstract translation: 半导体封装系统及其制造方法包括：具有接触焊盘的管芯; 具有大致梯形截面的引线指; 夹在引线指的顶部和侧面上的凸起，凸起连接到接触垫; 以及在引线指和芯片上的密封剂，具有引线指的底部的密封剂暴露。

公开(公告)号：US20120193132A1

公开(公告)日：2012-08-02

申请号：US13441550

申请日：2012-04-06

Applicant: Haengcheol Choi ,  Ki Youn Jang ,  Taewoo Kang ,  Il Kwon Shim

Inventor： Haengcheol Choi ,  Ki Youn Jang ,  Taewoo Kang ,  Il Kwon Shim

IPC: H05K1/16 ,  H05K3/30

CPC classification number: H01L24/06 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06142 ,  H01L2224/1403 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/4913

Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.

Abstract translation: 提供了一种电子系统，包括形成具有辐射图案化垫的衬底，将具有外部互连的电气装置安装在辐射图案化焊盘上，其中外部互连偏离辐射图案化衬垫，并将外部互连与辐射图案化衬垫对准。

公开(公告)号：US08129263B2

公开(公告)日：2012-03-06

申请号：US13178331

申请日：2011-07-07

Applicant: Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

Inventor： Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2924/2065 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.

Abstract translation: 半导体封装的制造方法包括：提供衬底; 将半导体管芯安装在基板上，半导体管芯具有管芯焊盘; 将引线安装在基板上; 在所述引导指的侧面附接支撑基座; 并且在芯片焊盘和支撑基座之间附接电线互连，电线互连在芯片焊盘上具有球接合，并且在支撑基座上具有针脚接合。

公开(公告)号：US20110298107A1

公开(公告)日：2011-12-08

申请号：US13211698

申请日：2011-08-17

Applicant: Ki Youn Jang ,  YoungMin Kim ,  Hyung Jun Jeon

Inventor： Ki Youn Jang ,  YoungMin Kim ,  Hyung Jun Jeon

IPC: H01L25/065 ,  H01L21/98

CPC classification number: H01L23/3128 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.

Abstract translation: 一种屏蔽层叠集成电路封装系统的制造方法，包括：形成具有第一基板和第一集成电路管芯的第一集成电路结构; 将屏蔽件安装在所述第一基板和所述第一集成电路管芯上; 在所述屏蔽上安装具有第二基板和第二集成电路管芯的第二集成电路结构; 以及形成用于覆盖所述第一集成电路管芯，所述屏蔽件和所述第二集成电路结构的封装封装。

公开(公告)号：US07772683B2

公开(公告)日：2010-08-10

申请号：US11608827

申请日：2006-12-09

Applicant: Ki Youn Jang ,  Jong-Woo Ha ,  Jong Wook Ju

Inventor： Ki Youn Jang ,  Jong-Woo Ha ,  Jong Wook Ju

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and the bottom surface, connecting a second internal interconnect between the second device and the bottom surface, and encapsulating the first device and the second device.

Abstract translation: 提供了一种堆叠集成电路封装包装系统，包括形成具有顶表面和底表面的基板，将第一装置安装在顶表面上方，以第一装置在偏移构造中堆叠第二装置，连接第一 在第一装置和底表面之间的内部互连，在第二装置和底表面之间连接第二内部互连，并封装第一装置和第二装置。

公开(公告)号：US07741726B2

公开(公告)日：2010-06-22

申请号：US12336141

申请日：2008-12-16

Applicant: Hyung Jun Jeon ,  Ki Youn Jang ,  Dae-Wook Yang

Inventor： Hyung Jun Jeon ,  Ki Youn Jang ,  Dae-Wook Yang

IPC: H01L23/29 ,  H01L23/02

CPC classification number: H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.

Abstract translation: 一种集成电路底部填充封装系统，包括提供具有分配端口的衬底，将第一集成电路管芯安装在衬底上，以及当衬底和第一集成电路管芯反相时，向分注端口提供底部填充物。

公开(公告)号：US07537962B2

公开(公告)日：2009-05-26

申请号：US11615922

申请日：2006-12-22

Applicant: Ki Youn Jang ,  YoungMin Kim ,  Hyung Jun Jeon

Inventor： Ki Youn Jang ,  YoungMin Kim ,  Hyung Jun Jeon

IPC: H01L21/00 ,  H01L23/02 ,  H05K1/14

CPC classification number: H01L23/3128 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A shielded stacked integrated circuit package system is provided including forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.

Abstract translation: 提供一种屏蔽堆叠集成电路封装系统，包括形成具有第一基板和第一集成电路管芯的第一集成电路结构; 将屏蔽件安装在所述第一基板和所述第一集成电路管芯上; 在所述屏蔽上安装具有第二基板和第二集成电路管芯的第二集成电路结构; 以及形成用于覆盖所述第一集成电路管芯，所述屏蔽件和所述第二集成电路结构的封装封装。

公开(公告)号：US07485502B2

公开(公告)日：2009-02-03

申请号：US11307315

申请日：2006-01-31

Applicant: Hyung Jun Jeon ,  Ki Youn Jang ,  Dae-Wook Yang

Inventor： Hyung Jun Jeon ,  Ki Youn Jang ,  Dae-Wook Yang

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted.

Abstract translation: 一种集成电路底部填充封装系统，包括提供具有分配端口的衬底，将第一集成电路管芯安装在衬底上，以及当衬底和第一集成电路管芯反相时，向分注端口提供底部填充物。

公开(公告)号：US07453156B2

公开(公告)日：2008-11-18

申请号：US11273635

申请日：2005-11-14

Applicant: Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

Inventor： Hun-Teak Lee ,  Jong-Kook Kim ,  Chul-Sik Kim ,  Ki-Youn Jang ,  Rajendra D. Pendse

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2924/2065 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554

Abstract: A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal.

Abstract translation: 芯片焊盘和键合指状物之间的引线键合互连包括在引线指的键合位置处的支撑基座，芯片焊盘上的球接合以及支撑基座上的线圈接合，其中引线指 在焊接点处小于支撑基座的直径。 此外，包括安装在多个引线键合并且电连接到基板的裸片的半导体封装，其中每个引线键合包括接合到模具上的焊盘的线球，并且在与基板上的支撑基座上接合 引线指的键位置，并且其中引线指在键合位置处的宽度小于支撑基座的直径。

公开(公告)号：US08703541B2

公开(公告)日：2014-04-22

申请号：US13441550

申请日：2012-04-06

Applicant: Haengcheol Choi ,  Ki Youn Jang ,  Taewoo Kang ,  Il Kwon Shim

Inventor： Haengcheol Choi ,  Ki Youn Jang ,  Taewoo Kang ,  Il Kwon Shim

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/06 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06142 ,  H01L2224/1403 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/4913

Abstract: An electronic system is provided including forming a substrate having a radiating patterned pad, mounting an electrical device having an external interconnect over the radiating patterned pad with the external interconnect offset from the radiating patterned pad, and aligning the external interconnect with the radiating patterned pad.

Abstract translation: 提供了一种电子系统，包括形成具有辐射图案化垫的衬底，将具有外部互连的电气装置安装在辐射图案化焊盘上，其中外部互连偏离辐射图案化衬垫，并将外部互连与辐射图案化衬垫对准。