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    Semiconductor wafer with improved step coverage along scribe lines
    4.
    发明授权
    Semiconductor wafer with improved step coverage along scribe lines 失效
    半导体晶片具有沿划线改善的台阶覆盖

    公开(公告)号：US5300816A

    公开(公告)日：1994-04-05

    申请号：US904613

    申请日：1992-06-26

    申请人： Jeungwoo Lee ,  Myoungseob Shim ,  Heonjong Shin

    发明人： Jeungwoo Lee ,  Myoungseob Shim ,  Heonjong Shin

    IPC分类号： H01L21/02 ,  H01L21/304 ,  H01L21/312 ,  H01L21/78 ,  H01L27/00 ,  H01L23/48 ,  H01L29/44 ,  H01L29/46

    CPC分类号： H01L21/312 ,  H01L21/3043 ,  H01L21/78

    摘要： A semiconductor wafer partitioned into a multiplicity of chip areas defined by a grid-like array of scribe lines inscribed into the surface of the wafer, wherein each scribe line is longitudinally bounded by respective field oxide layers formed in the surface of the wafer, to thereby define a scribe line region between adjacent chip areas. The wafer includes a multiplicity of integrated circuits formed in a corresponding multiplicity of the chip areas, respectively, each of the integrated circuits including a patterned, multilayer structure having a peripheral edge portion which extends into a respective one of the scribe line regions, wherein the peripheral edge portion of each multilayer structure has a multi-tiered cross-sectional profile, thereby ensuring adequate step coverage of the photoresist film which is applied to the individual layers of the multilayer structures when they are patterned during the wafer fabrication process.

    摘要翻译： 半导体晶片被划分为由刻划在晶片表面上的划线的格子状阵列限定的多个芯片区域，其中每个划线由在晶片表面形成的相应的场氧化物层纵向界定，从而 定义相邻芯片区域之间的划线区域。 晶片包括分别形成在相应多个芯片区域中的多个集成电路，每个集成电路包括图案化的多层结构，其具有延伸到相应的划线区域中的周边边缘部分，其中， 每个多层结构的周缘部分具有多层横截面轮廓，从而确保在晶片制造过程中图案化时施加到多层结构的各个层的光致抗蚀剂膜的足够的台阶覆盖。

    SEMICONDUCTOR DEVICES INCLUDING A GATE CORE AND A FIN ACTIVE CORE AND METHODS OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A GATE CORE AND A FIN ACTIVE CORE AND METHODS OF FABRICATING THE SAME 有权
    包括门芯和精细活动核心的半导体器件及其制造方法

    公开(公告)号：US20160111524A1

    公开(公告)日：2016-04-21

    申请号：US14820860

    申请日：2015-08-07

    申请人： Seungseok HA ,  Keunhee BAI ,  Kyounghwan YEO ,  Eunsil PARK ,  Heonjong SHIN

    发明人： Seungseok HA ,  Keunhee BAI ,  Kyounghwan YEO ,  Eunsil PARK ,  Heonjong SHIN

    IPC分类号： H01L29/66 ,  H01L21/762

    CPC分类号： H01L29/66795 ,  H01L21/76229 ,  H01L29/66545

    摘要： Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.

    摘要翻译： 提供半导体器件及其制造方法。 所述方法可以包括形成限定翅片有源区域的隔离区域，在隔离区域上形成牺牲场栅极图案，并在翅片有源区域上形成牺牲鳍栅极图案。 该方法还可以包括形成场栅切割区，其包括露出隔离区的表面的第一凹部和鳍片主动切割区，其包括暴露翅片有源区的表面的第二凹部，在第二凹部中形成翅片活动凹部 的翅片活动切割区域，并且通过在场浇口切割区域的第一凹部和翅片活动凹部中分别形成绝缘材料，分别形成场门芯和翅片活动芯。