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    SEMICONDUCTOR DEVICE INCLUDING HIGH VOLTAGE AND LOW VOLTAGE MOS DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING HIGH VOLTAGE AND LOW VOLTAGE MOS DEVICES 有权
    包括高电压和低电压MOS器件的半导体器件

    公开(公告)号：US20110151642A1

    公开(公告)日：2011-06-23

    申请号：US13039525

    申请日：2011-03-03

    申请人： ChanSam CHANG ,  Shigenobu MAEDA ,  HeonJong SHIN ,  ChangBong OH

    发明人： ChanSam CHANG ,  Shigenobu MAEDA ,  HeonJong SHIN ,  ChangBong OH

    IPC分类号： H01L21/265

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

    摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

    摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。

    Asymmetric semiconductor device and fabrication method
    3.
    发明申请
    Asymmetric semiconductor device and fabrication method 有权
    非对称半导体器件及其制造方法

    公开(公告)号：US20070138592A1

    公开(公告)日：2007-06-21

    申请号：US11523068

    申请日：2006-09-19

    申请人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

    发明人： ChanSam Chang ,  Shigenobu Maeda ,  HeonJong Shin ,  ChangBong Oh

    IPC分类号： H01L29/00

    CPC分类号： H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0692 ,  H01L29/1079 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

    摘要： Methods and devices for forming both high-voltage and low-voltage transistors on a common substrate using a reduced number of processing steps are disclosed. An exemplary method includes forming at least a first high-voltage transistor well and a first low-voltage transistor well on a common substrate separated by an isolation structure extending a first depth into the substrate, using a first mask and first implantation process to simultaneously implant a doping material of a first conductivity type into a channel region of the low-voltage transistor well and a drain region for the high-voltage transistor well.

    摘要翻译： 公开了使用减少数量的处理步骤在公共基板上形成高压和低压晶体管的方法和装置。 一种示例性方法包括使用第一掩模和第一注入工艺同时注入在至少第一高电压晶体管阱和第一低电压晶体管阱上形成阱，所述公共衬底由隔离结构隔开，所述隔离结构将第一深度延伸到衬底中 第一导电类型的掺杂材料进入低压晶体管阱的沟道区域和用于高压晶体管阱的漏极区域。