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公开(公告)号：US20240363156A1
公开(公告)日：2024-10-31
申请号：US18770651
申请日：2024-07-12
发明人： Chao-Chun Lu , Chun Shiah , Bor-Doou Rong
IPC分类号： G11C11/4074 , G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4074 , G11C11/406 , G11C11/4085 , G11C11/4091 , G11C11/4094
摘要： The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.
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公开(公告)号：US12074205B2
公开(公告)日：2024-08-27
申请号：US16991044
申请日：2020-08-12
发明人： Chao-Chun Lu
IPC分类号： H01L29/417 , H01L21/285 , H01L21/762 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/45 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41766 , H01L21/28518 , H01L21/76224 , H01L27/0921 , H01L29/0653 , H01L29/0847 , H01L29/45 , H01L29/66492 , H01L29/7833
摘要： A transistor structure includes a semiconductor substrate, agate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The channel region includes a first terminal and a second terminal. The first conductive region is electrically coupled to the first terminal of the channel region, and the first conductive region includes a first metal containing region under the semiconductor surface.
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公开(公告)号：US12068020B2
公开(公告)日：2024-08-20
申请号：US17574494
申请日：2022-01-12
发明人： Chao-Chun Lu , Chun Shiah , Bor-Doou Rong
IPC分类号： G11C11/4074 , G11C11/406 , G11C11/408 , G11C11/4091 , G11C11/4094
CPC分类号： G11C11/4074 , G11C11/406 , G11C11/4085 , G11C11/4091 , G11C11/4094
摘要： The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.
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公开(公告)号：US20240153540A1
公开(公告)日：2024-05-09
申请号：US18408510
申请日：2024-01-09
发明人： Chao-Chun Lu
CPC分类号： G11C5/063 , H01L29/0653 , H10B12/0335 , H10B12/053 , H10B12/315 , H10B12/34 , H10B12/482 , H10B12/488
摘要： A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.
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公开(公告)号：US20240128150A1
公开(公告)日：2024-04-18
申请号：US18473999
申请日：2023-09-25
发明人： HO-MING TONG , CHAO-CHUN LU
IPC分类号： H01L23/367 , H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L23/3675 , H01L23/49822 , H01L23/49838 , H01L24/08 , H01L24/16 , H01L25/0655 , H01L2224/08137 , H01L2224/08146 , H01L2224/16157 , H01L2224/16227 , H01L2924/1433 , H01L2924/1436 , H10B80/00
摘要： A semiconductor package is provided, which includes a processor die powered by either a front-side or a backside power delivery network, a plurality of memory dies and control dies stacked over the processor die, a plurality of high-thermal-conductivity interconnects located between and/or placed side-by-side with the dies, a substrate carrying all the dies with the substrate having a first cavity allowing a liquid to pass through, and a cold plate disposed over and in direct thermal contact with the top dies with the cold plate having a second cavity configured to connect to the first cavity and allowing the liquid to flow between the first and second cavities. This semiconductor package can be configured to go beyond the traditional single-sided interconnection and cooling topologies to enable dual- or multi-sided cooling, power supply, and signaling.
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公开(公告)号：US20240047298A1
公开(公告)日：2024-02-08
申请号：US18231408
申请日：2023-08-08
发明人： Ho-Ming TONG , Wei YEN , Chao-Chun LU
IPC分类号： H01L23/373 , H01L25/065 , H01L23/48 , H01L23/367 , H01L23/473
CPC分类号： H01L23/3732 , H01L25/0657 , H01L23/481 , H01L23/367 , H01L23/473 , H01L2225/06589
摘要： A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.
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公开(公告)号：US20240047297A1
公开(公告)日：2024-02-08
申请号：US17970964
申请日：2022-10-21
发明人： Ho-Ming TONG , Wei YEN , Chao-Chun LU
IPC分类号： H01L23/373 , H01L23/00 , H01L23/29 , H01L23/31 , H01L21/56
CPC分类号： H01L23/3732 , H01L24/80 , H01L24/08 , H01L24/05 , H01L23/291 , H01L23/298 , H01L23/3185 , H01L21/566 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2224/05687 , H01L2224/05691 , H01L2224/05644 , H01L2224/08145 , H01L2924/1033 , H01L2924/10272 , H01L2924/10254 , H01L2924/10253 , H01L2924/1011 , H01L2224/08225
摘要： A method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein each diamond block has a dimension smaller than the predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; or attaching the first diamond composite wafer to a second semiconductor substrate with the predetermined diameter to form the second diamond composite wafer, or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.
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公开(公告)号：US11894098B2
公开(公告)日：2024-02-06
申请号：US17213133
申请日：2021-03-25
发明人： Der-Min Yuan , Yen-An Chang , Wei-Ming Huang
IPC分类号： G11C7/10 , G11C11/4074 , G06F12/0882 , G06F3/06 , G06F12/02 , G06F13/42 , G06F12/06 , G06F12/0866 , G11C11/406
CPC分类号： G11C7/1075 , G11C11/4074 , G06F3/061 , G06F3/0653 , G06F3/0656 , G06F12/0238 , G06F12/063 , G06F12/0692 , G06F12/0866 , G06F12/0882 , G06F13/4221 , G06F13/4278 , G11C11/40615 , Y02D10/00
摘要： A dynamic random access memory applied to an embedded display port includes a memory core unit, a peripheral circuit unit, and an input/output unit. The memory core unit is used for operating in a first predetermined voltage. The peripheral circuit unit is electrically connected to the memory core unit for operating in a second predetermined voltage, where the second predetermined voltage is lower than 1.1V. The input/output unit is electrically connected to the memory core unit and the peripheral circuit unit for operating in a third predetermined voltage, where the third predetermined voltage is lower than 1.1V.
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9.发明公开公开(公告)号：US20240030347A1
公开(公告)日：2024-01-25
申请号：US18376839
申请日：2023-10-05
发明人： Chao-Chun Lu
IPC分类号： H01L29/78 , H01L27/088 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7851 , H01L27/0886 , H01L29/0649 , H01L29/1033
摘要： A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.
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10.发明公开公开(公告)号：US20240027494A1
公开(公告)日：2024-01-25
申请号：US18355255
申请日：2023-07-19
发明人： HO-MING TONG , CHAO-CHUN LU
CPC分类号： G01R1/07342 , G01R1/06783 , G01R3/00
摘要： A probe card system is provided. The probe card system, including a tester assembly, a probe head body configured to couple with the tester assembly, a first interconnection structure on a first side of the probe head body, and a probe layer structure on the first interconnection structure on the first side of the probe head body which is configured to engage with a wafer under test (WUT). The probe layer structure includes a sacrificial layer in connection with the first interconnection structure, a bonding layer in connection with the sacrificial layer, and a plurality of probe tips each in connection with respective conductive patterns exposed from the bonding layer and electrically coupled to the first interconnection structure. The sacrificial layer allows removal of the bonding layer and the plurality of probe tips via an etching operation. A method of manufacturing a probe card system is also provided.
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