公开(公告)号：US12206447B2

公开(公告)日：2025-01-21

申请号：US17355200

申请日：2021-06-23

Applicant: Altera Corporation

Inventor： Nima Safari ,  Richard Maiden

IPC: H04B1/7107 ,  H04B1/00 ,  H04B1/62

Abstract: A signal processing device includes a filter, configured to receive first data representing a signal for wireless transmission, modify the first data in a filter operation, and output second data as the modified first data; a peak detector, configured to detect third data representing a peak of the signal, wherein the third data are a subset of the first data; a signal canceller, configured to receive the third data and to generate fourth data representing a cancellation signal corresponding to the peak of the signal; and a peak modifier, configured to receive the second data and the fourth data, and to generate fifth data using the second data and the fourth data, wherein the fifth data represent the signal with a modified peak.

公开(公告)号：US20250022495A1

公开(公告)日：2025-01-16

申请号：US18904611

申请日：2024-10-02

Applicant: Altera Corporation

Inventor： Wee Leam Teoh

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/08

Abstract: An integrated circuit includes a memory bit cell having a transistor coupled to a data line and a write pulse generation circuit coupled to the memory bit cell. The write pulse generation circuit generates a pulse in a word line signal that controls the transistor. The write pulse generation circuit adjusts a width of the pulse in the word line signal based on a write time of a write operation to the memory bit cell performed through the data line and the transistor.

公开(公告)号：US20240412799A1

公开(公告)日：2024-12-12

申请号：US18809696

申请日：2024-08-20

Applicant: Altera Corporation

Inventor： Kok Wah Khor ,  Rajiv Kumar

IPC: G11C29/36 ,  G11C7/10 ,  G11C29/12

Abstract: An integrated circuit includes memory circuits, a selector circuit, a bus coupled to the selector circuit, and a controller circuit. The controller circuit provides test signals from the controller circuit through the bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode. Each of the memory circuits can include a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.

公开(公告)号：US20240396579A1

公开(公告)日：2024-11-28

申请号：US18792306

申请日：2024-08-01

Applicant: Altera Corporation

Inventor： Dan Pritsker ,  Colman Cheung ,  Benjamin Esposito

IPC: H04B1/04 ,  H01Q13/08 ,  H04B7/06 ,  H04L27/20

Abstract: An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, and mixer circuits. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted into radio frequency (RF) signals. The receiver includes mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). RF signals are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

公开(公告)号：US20240386102A1

公开(公告)日：2024-11-21

申请号：US18789413

申请日：2024-07-30

Applicant: Altera Corporation

Inventor： Mohamed Hassan

IPC: G06F21/55 ,  G06F3/06

Abstract: An integrated circuit includes a control circuit configured to send a first command for accessing a row of a memory circuit to the memory circuit during a refresh cycle of the memory circuit. The integrated circuit also includes a first buffer circuit configured to store data accessed from the row of the memory circuit in response to the first command. The integrated circuit also includes a second buffer circuit configured to store an address for the data. The control circuit services a second command for accessing the row during the refresh cycle by accessing the first buffer circuit using the address stored in the second buffer circuit and by preventing the memory circuit from performing an activation command of the row in response to the second command.

公开(公告)号：US12147377B2

公开(公告)日：2024-11-19

申请号：US18299662

申请日：2023-04-12

Applicant: Altera Corporation

Inventor： Gary Brian Wallichs ,  Keith Duwel ,  Cora Lynn Mau

IPC: G06F13/42 ,  G06F5/06 ,  H04L69/14 ,  H04L49/25

Abstract: Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.

公开(公告)号：US20240356548A1

公开(公告)日：2024-10-24

申请号：US18763451

申请日：2024-07-03

Applicant: Altera Corporation

Inventor： Pai Ho Bong ,  Sean Woei Voon ,  Shyue Loong Lim ,  Chong Xin Tan

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018528 ,  H03K19/018585

Abstract: An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer circuit is configurable to cause the second transistor to be controlled by a second voltage during the data output mode of operation and to couple a second control input of the second transistor to the external pad during the hot-socket protection mode of operation.

公开(公告)号：US20240321716A1

公开(公告)日：2024-09-26

申请号：US18680058

申请日：2024-05-31

Applicant: Altera Corporation

Inventor： Md Altaf Hossain ,  Atul Maheshwari ,  Mahesh Kumashikar ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

IPC: H01L23/498 ,  G06F30/31 ,  G06F115/10

CPC classification number: H01L23/49838 ,  G06F30/31 ,  G06F2115/10

Abstract: An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.

公开(公告)号：US20240241994A1

公开(公告)日：2024-07-18

申请号：US18620757

申请日：2024-03-28

Applicant: Altera Corporation

Inventor： Michael Neve de Mevergnies

IPC: G06F21/86 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F21/86 ,  G06F21/602 ,  G06F21/79 ,  G06F2221/2143

Abstract: Anti-tamper systems and methods for protecting integrated circuit devices are provided. An integrated circuit device making use of an anti-tamper system may include memory and a device manager. The memory may store a count of resets of the integrated circuit device having a duration less than a threshold reset duration. The device manager may perform an anti-tamper operation when the count of resets exceeds a threshold number of resets.

公开(公告)号：US12026008B2

公开(公告)日：2024-07-02

申请号：US17973428

申请日：2022-10-25

Applicant: Intel Corporation

Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

IPC: G06F1/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: G06F1/10 ,  H01L23/3114 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14515 ,  H01L2224/16227 ,  H01L2224/14515 ,  H01L2924/00012

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.