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    Joint channel filtering and crest factor reduction architecture
    1.
    发明授权
    Joint channel filtering and crest factor reduction architecture 有权

    公开(公告)号：US12206447B2

    公开(公告)日：2025-01-21

    申请号：US17355200

    申请日：2021-06-23

    Applicant: Altera Corporation

    Inventor： Nima Safari ,  Richard Maiden

    IPC: H04B1/7107 ,  H04B1/00 ,  H04B1/62

    Abstract: A signal processing device includes a filter, configured to receive first data representing a signal for wireless transmission, modify the first data in a filter operation, and output second data as the modified first data; a peak detector, configured to detect third data representing a peak of the signal, wherein the third data are a subset of the first data; a signal canceller, configured to receive the third data and to generate fourth data representing a cancellation signal corresponding to the peak of the signal; and a peak modifier, configured to receive the second data and the fourth data, and to generate fifth data using the second data and the fourth data, wherein the fifth data represent the signal with a modified peak.

    Hybrid architecture for signal processing
    4.
    发明授权
    Hybrid architecture for signal processing 有权
    用于信号处理的混合架构

    公开(公告)号：US09553591B2

    公开(公告)日：2017-01-24

    申请号：US14492717

    申请日：2014-09-22

    Applicant: Altera Corporation

    Inventor： Steven Perry ,  Martin Langhammer ,  Richard Maiden

    IPC: G06F17/10 ,  H03K19/177 ,  G06F1/02 ,  G06F17/50

    CPC classification number: H03K19/17748 ,  G06F1/02 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/1776

    Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

    Abstract translation: 配置可编程集成电路的系统和方法。 信号处理加速器（SPAs）阵列包含在可编程集成电路中。 SPA阵列与现场可编程门阵列（FPGA）分离，并且SPA阵列被配置为从FPGA接收输入数据，并且可编程为至少对输入数据执行滤波功能以获得输出数据。

    Methods and apparatus for adjusting transmit signal clipping thresholds
    5.
    发明授权
    Methods and apparatus for adjusting transmit signal clipping thresholds 有权
    调整发射信号限幅阈值的方法和装置

    公开(公告)号：US09337782B1

    公开(公告)日：2016-05-10

    申请号：US14283703

    申请日：2014-05-21

    Applicant: Altera Corporation

    Inventor： Volker Mauer ,  Nima Safari ,  Shahin Gheitanchi ,  Richard Maiden

    IPC: H04B1/04 ,  H03F1/32 ,  H03F3/19 ,  H03F3/24 ,  H04L27/34

    CPC classification number: H03F1/3247 ,  H03F1/3241 ,  H03F3/19 ,  H03F3/245 ,  H03F2200/435 ,  H03F2200/451 ,  H03F2201/3227 ,  H04B1/0475 ,  H04B2001/0425 ,  H04L25/03343 ,  H04L27/3411

    Abstract: Integrated circuits are provided with wireless communications circuitry having digital predistortion (DPD) circuitry, peak canceling circuitry, a power amplifier, and signal conditioning circuitry for controlling the DPD and peak canceling circuitry. The peak canceling circuitry may receive transmit signals and may clip peaks in the transmit signals that exceed a magnitude threshold value. The DPD circuitry may compensate for non-linear characteristics of the power amplifier by outputting a predistorted version of the clipped transmit signals. The power amplifier may receive the predistorted signals and may perform amplification to generate amplified signals. The signal conditioning circuitry may identify power transfer characteristics of the power amplifier and DPD circuitry using the predistorted signals and the amplified signals. The signal conditioning circuitry may update the magnitude threshold value imposed by the peak canceling threshold based on the identified power transfer characteristics to mitigate out-of-band spectral regrowth in the predistorted signals.

    Abstract translation: 集成电路配备有具有数字预失真（DPD）电路，峰值消除电路，功率放大器和用于控制DPD和峰值消除电路的信号调节电路的无线通信电路。 峰值消除电路可以接收发射信号，并且可以在超过幅度阈值的发射信号中削波峰值。 DPD电路可以通过输出限幅发送信号的预失真版本来补偿功率放大器的非线性特性。 功率放大器可以接收预失真信号，并且可以执行放大以产生放大的信号。 信号调节电路可以使用预失真信号和放大信号来识别功率放大器和DPD电路的功率传输特性。 信号调节电路可以基于所识别的功率传输特性来更新由峰值消除阈值施加的幅度阈值，以减轻预失真信号中的带外频谱再生长。

    HYBRID ARCHITECTURE FOR SIGNAL PROCESSING
    6.
    发明申请
    HYBRID ARCHITECTURE FOR SIGNAL PROCESSING 有权
    混合信号处理结构

    公开(公告)号：US20150088948A1

    公开(公告)日：2015-03-26

    申请号：US14492717

    申请日：2014-09-22

    Applicant: Altera Corporation

    Inventor： Steven Perry ,  Martin Langhammer ,  Richard Maiden

    IPC: H03K19/177 ,  G06F1/02 ,  G06F17/50

    CPC classification number: H03K19/17748 ,  G06F1/02 ,  G06F17/505 ,  G06F17/5054 ,  H03K19/1776

    Abstract: Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data.

    Abstract translation: 配置可编程集成电路的系统和方法。 信号处理加速器（SPAs）阵列包含在可编程集成电路中。 SPA阵列与现场可编程门阵列（FPGA）分离，并且SPA阵列被配置为从FPGA接收输入数据，并且可编程为至少对输入数据执行滤波功能以获得输出数据。

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