公开(公告)号：US20240386102A1

公开(公告)日：2024-11-21

申请号：US18789413

申请日：2024-07-30

Applicant: Altera Corporation

Inventor： Mohamed Hassan

IPC: G06F21/55 ,  G06F3/06

Abstract: An integrated circuit includes a control circuit configured to send a first command for accessing a row of a memory circuit to the memory circuit during a refresh cycle of the memory circuit. The integrated circuit also includes a first buffer circuit configured to store data accessed from the row of the memory circuit in response to the first command. The integrated circuit also includes a second buffer circuit configured to store an address for the data. The control circuit services a second command for accessing the row during the refresh cycle by accessing the first buffer circuit using the address stored in the second buffer circuit and by preventing the memory circuit from performing an activation command of the row in response to the second command.