公开(公告)号：US20240412799A1

公开(公告)日：2024-12-12

申请号：US18809696

申请日：2024-08-20

Applicant: Altera Corporation

Inventor： Kok Wah Khor ,  Rajiv Kumar

IPC: G11C29/36 ,  G11C7/10 ,  G11C29/12

Abstract: An integrated circuit includes memory circuits, a selector circuit, a bus coupled to the selector circuit, and a controller circuit. The controller circuit provides test signals from the controller circuit through the bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode. Each of the memory circuits can include a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.