公开(公告)号：US09147586B2

公开(公告)日：2015-09-29

申请号：US14083452

申请日：2013-11-19

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Jun Lu ,  Kai Liu ,  Yan Xun Xue

IPC分类号： H01L23/495 ,  H01L23/34 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/07 ,  H01L23/31

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L25/07 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

摘要翻译： 具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。 制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅 切割或磨削。

公开(公告)号：US09041172B1

公开(公告)日：2015-05-26

申请号：US14105473

申请日：2013-12-13

申请人： Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

发明人： Zhi Qiang Niu ,  Hamza Yilmaz ,  Jun Lu ,  Fei Wang

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/84 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

摘要翻译： 本发明一般涉及一种半导体器件，更具体地，涉及优化功率半导体器件的蠕变寿命距离及其制备方法。 功率半导体器件包括具有管芯焊盘的芯片安装单元和以等间距方式靠近管芯焊盘的一个侧边缘并排设置的多个引线，附接在管芯焊盘上的半导体芯片，以及 塑料包装体覆盖模片，半导体芯片，其中塑料包装体包括覆盖引线的引线肩部的至少一部分的塑料延伸部分，以在半导体器件的端子之间获得更好的电气安全距离，因此电压 设备的爬坡距离增加。

公开(公告)号：US09006870B2

公开(公告)日：2015-04-14

申请号：US13955206

申请日：2013-07-31

申请人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

发明人： Xiaotian Zhang ,  Hua Pan ,  Ming-Chen Lu ,  Jun Lu ,  Hamza Yilmaz

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/56 ,  H01L21/78 ,  H01L22/14 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/27 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/07 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/118 ,  H01L2224/13022 ,  H01L2224/32245 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40145 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/84801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the meal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.

摘要翻译： 堆叠多芯片封装结构包括引线框架，安装在引线框架上的第一半导体芯片，安装在引线框架上的第二半导体芯片翻转芯片，安装在第一和第二半导体芯片顶部的金属夹子和 第三个半导体芯片堆叠在餐夹上; 将第三半导体芯片上的电极电连接到第一和第二半导体芯片和引线框架的引脚的接合线; 塑料成型封装引线框架，芯片和金属夹。

公开(公告)号：US08969950B2

公开(公告)日：2015-03-03

申请号：US13306067

申请日：2011-11-29

申请人： Ji Pan

发明人： Ji Pan

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/861 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/47

CPC分类号： H01L29/66734 ,  H01L21/26586 ,  H01L21/28238 ,  H01L29/0623 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/47 ,  H01L29/66128 ,  H01L29/66143 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

摘要： A MOSFET device and fabrication method are disclosed. The MOSFET has a drain in chip plane with an epitaxial layer overlay atop. The MOSFET further comprises: a Kelvin-contact body and an embedded Kelvin-contact source; a trench gate extending into the epitaxial layer; a lower contact trench extending through the Kelvin-contact source and at least part of the Kelvin-contact body defining respectively a vertical source-contact surface and a vertical body-contact surface; a patterned dielectric layer atop the Kelvin-contact source and the trench gate; a patterned top metal layer. As a result: a planar ledge is formed atop the Kelvin-contact source; the MOSFET device exhibits a lowered body Kelvin contact impedance and, owing to the presence of the planar ledge, a source Kelvin contact impedance that is lower than an otherwise MOSFET device without the planar ledge; and an integral parallel Schottky diode is also formed.

摘要翻译： 公开了MOSFET器件和制造方法。 MOSFET具有在芯片平面上的漏极，外延层覆盖在顶部。 MOSFET还包括：开尔文接触体和嵌入式开尔文接触源; 延伸到外延层中的沟槽栅; 延伸穿过开尔文接触源的下接触沟槽和分别定义垂直的源极接触表面和垂直体接触表面的开尔文接触体的至少一部分; 位于开尔文接触源和沟槽栅极顶部的图案化介电层; 图案顶层金属层。 结果：在开尔文接触源顶部形成一个平面凸缘; MOSFET器件表现出较低的体积开尔文接触阻抗，并且由于存在平面凸缘，源开尔文接触阻抗低于不具有平面凸缘的另外的MOSFET器件; 并且还形成一个整体的并联肖特基二极管。

公开(公告)号：US08933549B2

公开(公告)日：2015-01-13

申请号：US14106654

申请日：2013-12-13

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Kai Liu ,  Lei Shi ,  Jun Lu ,  Anup Bhalla

IPC分类号： H01L23/52 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49589 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/24247 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/92246 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe.

摘要翻译： 双引线框多芯片封装包括具有第一管芯焊盘的第一引线框架和具有第二管芯焊盘的第二引线框架; 安装在用作高边MOSFET的第一芯片焊盘上的第一芯片和安装在用作低端MOSFET的第二芯片焊盘上的第二芯片。 封装还可以包括配置为安装在第一裸片焊盘上或与第一芯片集成的第三芯片的旁路容量。 封装还可以包括形成为一体结构的三维连接板作为第二芯片焊盘，用于将第一芯片的顶部接触区域电连接到第二芯片的底部接触区域。 顶部连接板将第二芯片的顶部接触区域和第三芯片的顶部接触区域连接到第一引线框架的外部引脚。

公开(公告)号：US08796858B2

公开(公告)日：2014-08-05

申请号：US13488424

申请日：2012-06-04

申请人： Tao Feng ,  Yueh-Se Ho

发明人： Tao Feng ,  Yueh-Se Ho

IPC分类号： H01L23/48

CPC分类号： H01L21/561 ,  H01L23/142 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/92 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness TPSD. The FDC has patterned back-face carrier metallizations contacting the front-face device metallization pads, patterned front-face carrier metallization pads and numerous parallelly connected through-carrier conductive vias respectively connecting the back-face carrier metallizations to the front-face carrier metallization pads. The FDC thickness TFDC is large enough to provide structural rigidity to the VSLCPSD. The diminishing thickness TPSD effects a low back substrate resistance and the through-carrier conductive vias effect a low front-face contact resistance to the front-face device metallization pads.

摘要翻译： 公开了一种实际上无衬底的复合功率半导体器件（VSLCPSD）和方法。 VSLCPSD具有功率半导体器件（PSD），由载体材料制成的正面器件载体（FDC）和中间键合层（IBL）。 载体和IBL材料都可以是导电的或不导电的。 PSD具有后衬底部分，具有图案化前面装置金属化焊盘的前半导体器件部分和实际上减小的厚度TPSD。 FDC具有接触前表面器件金属化焊盘，图案化前面载体金属化焊盘和多个并联连接的贯穿载体导电通孔的图案化背面载体金属化，其分别将背面载体金属化物连接到前面载体金属化焊盘 。 FDC厚度TFDC足够大以向VSLCPSD提供结构刚度。 厚度减小的TPSD会影响背面的底层电阻，并且贯穿载体的导电通孔会对前面装置的金属化焊盘产生低的前端接触电阻。

公开(公告)号：US08709893B2

公开(公告)日：2014-04-29

申请号：US13216122

申请日：2011-08-23

申请人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

发明人： Yi Su ,  Daniel Ng ,  Anup Bhalla ,  Jun Lu

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/83 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/8309 ,  H01L2224/83141 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.

摘要翻译： 本发明涉及功率半导体器件及其制备方法。 特别地，本发明旨在提供一种降低功率MOSFET的Rdson（漏源电阻）的基板贡献的方法以及通过该方法制造的功率MOSFET器件。 通过在Si衬底的底部形成一个或多个底部沟槽，有效地降低归因于衬底的功率MOSFET器件的导通电阻。 与具有底槽的衬底互补的匹配引线框架底座进一步改善了功率MOSFET器件的封装。

公开(公告)号：US20140085760A1

公开(公告)日：2014-03-27

申请号：US13628602

申请日：2012-09-27

申请人： ALPHA & OMEGA SEMICONDUCTOR, INC.

发明人： Sik K. Lui

IPC分类号： H02H3/20

CPC分类号： H03K17/0822 ,  H01L27/0255 ,  H01L27/0266 ,  H03K17/08

摘要： A protection circuit for a power transistor includes a first transistor connected in parallel with the power transistor and having a control terminal connected to a first power supply voltage through a first resistive element; and a first set of diodes connected between a first terminal and a control terminal of the first transistor. In operation, the voltage at the first terminal of the first transistor is clamped to a clamp voltage and the first transistor is turned on to conduct current in a forward conduction mode when an over-voltage condition occurs at a first terminal of the power transistor.

摘要翻译： 用于功率晶体管的保护电路包括与功率晶体管并联连接并具有通过第一电阻元件连接到第一电源电压的控制端的第一晶体管; 以及连接在第一晶体管的第一端子和控制端子之间的第一组二极管。 在操作中，当在功率晶体管的第一端子处发生过电压状态时，第一晶体管的第一端子处的电压被钳位到钳位电压，并且第一晶体管导通以导通正向导通模式的电流。

公开(公告)号：US08669650B2

公开(公告)日：2014-03-11

申请号：US13244256

申请日：2011-09-23

申请人： Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

发明人： Xiaotian Zhang ,  Hamza Yilmaz ,  Jun Lu ,  Xiaoguang Zeng ,  Ming-Chen Lu

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/49524 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/84 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/3701 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40106 ,  H01L2224/40135 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.

摘要翻译： 一种半导体器件封装，包括具有包括第一芯片安装区域和第二芯片安装区域的模板的引线框架，形成在第一芯片安装区域中的凹部区域和形成在凹部区域中的多个金属柱，凹口将 第一芯片安装区域横向延伸的横向基部和纵向延伸的纵向基部，并且将凹部区域分离成形成在横向基部中的横向凹部和形成在纵向基部中的纵向凹部; 连接到外部销的横向延伸部分的一部分延伸到凹口内部的一部分。

公开(公告)号：US08643137B2

公开(公告)日：2014-02-04

申请号：US13488350

申请日：2012-06-04

申请人： Shekar Mallikarjunaswamy ,  Amit Paul

发明人： Shekar Mallikarjunaswamy ,  Amit Paul

IPC分类号： H01L23/58 ,  H01L29/66

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region.

摘要翻译： 公开了一种短沟道横向MOSFET（LMOS）和方法，其具有用于降低通道导通电阻同时保持高穿透电压的互穿漏极体突起（IDBP）。 LMOS包括较低的器件体积层; 上部源极和上部漏极区域位于下部器件体层的顶部; 上部源极和上部漏极区都与下部器件本体层之间的中间上部区域接触; 上排水区和上体区均形成排水体界面; 排水体接口具有IDBP结构，其中表面排出突起位于掩埋体突起的顶部，同时露出上身体区域的顶部体表面积; 栅极氧化物栅极电极双层，其设置在形成LMOS的上部主体区域的顶部，其具有由在上部源区域和上部漏极区域之间描绘的顶部体表面积的水平长度限定的短沟道长度。