公开(公告)号：US20050229049A1

公开(公告)日：2005-10-13

申请号：US11148835

申请日：2005-06-09

Applicant: Hansel Collins

Inventor： Hansel Collins

IPC: H04L7/00 ,  G06F11/00 ,  G06K20060101 ,  G06K1/04 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  H04L25/14

CPC classification number: H04L25/14

Abstract: A system performs a two-step skew compensation procedure by first correcting for any phase error alignment between a parallel link clock and data signal edges of each data channel, thereby allowing the received data bits to be correctly sampled. Then, a second step is performed to “word-align” the bits into the original format, which is accomplished with a Skew Synchronizing Marker (SSM) byte in a data FIFO of each data channel. The SSM byte is transmitted on each data channel and terminates the skew compensation procedure. When the SSM byte is detected by logic in the data FIFO of each data channel, the data FIFO employs the SSM byte to initialize the read and write pointers to properly align the output data.

Abstract translation: 系统通过首先校正并行链路时钟和每个数据信道的数据信号边缘之间的任何相位误差对准来执行两步偏移补偿过程，从而允许接收到的数据位被正确采样。 然后，执行第二步以将这些位“字对齐”为原始格式，这是通过每个数据通道的数据FIFO中的歪斜同步标记（SSM）字节来实现的。 在每个数据通道上传输SSM字节，并终止偏斜补偿程序。 当每个数据通道的数据FIFO中的逻辑检测到SSM字节时，数据FIFO采用SSM字节来初始化读和写指针，以正确对齐输出数据。

公开(公告)号：US06954490B2

公开(公告)日：2005-10-11

申请号：US10162974

申请日：2002-06-05

Applicant: Kevin T. Chan

Inventor： Kevin T. Chan

IPC: H04B1/38 ,  H04B3/00 ,  H04B3/23 ,  H04B15/00 ,  H04J11/00 ,  H04L5/16 ,  H04L12/10 ,  H04L25/00 ,  H04L25/02 ,  H04L25/03 ,  H04L25/08 ,  H04L25/14 ,  H04L25/49 ,  H04L27/00 ,  H04L27/04

CPC classification number: H04L25/08 ,  H04B3/23 ,  H04B3/32 ,  H04L12/10 ,  H04L25/0276 ,  H04L25/0282 ,  H04L25/0286 ,  H04L25/03834 ,  H04L25/14

Abstract: A power efficient and reduced electromagnetic interference (EMI) emissions transmitter for unshielded twisted pair (UTP) data communication applications. Transmit data is interpolated by N and processed by a digital filter to obtain the pulse shape required by the particular communication application. The digital filter output data is converted to a current-mode analog waveform by a digital-to-analog converter (DAC). The digital filter is integrated with the DAC binary decoder in a memory device such as a ROM with time multiplexed output. When implemented in such manner, the logical implementation and memory replaces digital filtering circuits, DAC decoding logic circuit and re-synchronization logic circuits that are conventionally implemented in hardware. Thus, the hardware functionality of these circuits is rendered into arithmetic form and implemented in a memory device.

Abstract translation: 用于非屏蔽双绞线（UTP）数据通信应用的功率高效和降低的电磁干扰（EMI）发射器。 发送数据由N内插并由数字滤波器处理以获得特定通信应用所需的脉冲形状。 数字滤波器输出数据通过数/模转换器（DAC）转换为电流模式模拟波形。 数字滤波器与DAC二进制解码器集成在诸如具有时间复用输出的ROM的存储器件中。 当以这种方式实现时，逻辑实现和存储器替代了常规地以硬件实现的数字滤波电路，DAC解码逻辑电路和重新同步逻辑电路。 因此，这些电路的硬件功能被呈现为算术形式并在存储器件中实现。

公开(公告)号：US20050211878A1

公开(公告)日：2005-09-29

申请号：US11083050

申请日：2005-03-17

Applicant: Karim-Thomas Taghizadeh-Kaschani ,  Jose Martinez

Inventor： Karim-Thomas Taghizadeh-Kaschani ,  Jose Martinez

IPC: H01J40/14 ,  H04L25/02 ,  H04L25/08 ,  H04L25/14 ,  H04L25/40

CPC classification number: H04L25/0292 ,  H04L25/0272 ,  H04L25/14

Abstract: The invention relates to a receiver arrangement for a push-pull transmission method. First and second signal detectors, to which a first input signal is fed provide first and second detector signals depending on a comparison of the first input signal with a detector threshold. Third and fourth signal detectors, to which a second input signal is fed provide third and fourth detector signals depending on a comparison of the second input signal with a detector threshold. The first and third detector signals are respectively fed to a data input of a first and second buffer store The second and fourth detector signals are respectively fed to a reset input of the first and second buffer store. The first and second buffer store are designed for buffer-storing signal pulses contained in the first and second detector signals and forwarding them to a respective output for subsequent further processing in time-delayed fashion after a first delay duration.

Abstract translation: 本发明涉及一种用于推挽传输方法的接收器装置。 第一和第二信号检测器，其中馈送第一输入信号根据第一输入信号与检测器阈值的比较而提供第一和第二检测器信号。 根据第二输入信号与检测器阈值的比较，馈送第二输入信号的第三和第四信号检测器提供第三和第四检测器信号。 第一和第三检测器信号分别馈送到第一和第二缓冲存储器的数据输入端。第二和第四检测器信号分别馈送到第一和第二缓冲存储器的复位输入。 第一和第二缓冲存储器被设计用于缓冲存储包含在第一和第二检测器信号中的信号脉冲，并且将它们转发到相应的输出端，以便在第一延迟持续时间之后以时间延迟的方式进行随后的进一步处理。

公开(公告)号：US20050210308A1

公开(公告)日：2005-09-22

申请号：US10802634

申请日：2004-03-17

Applicant: Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

Inventor： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC: G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

Abstract: A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

Abstract translation: 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：US20050190875A1

公开(公告)日：2005-09-01

申请号：US10801103

申请日：2004-03-15

Applicant: Neil Feiereisel ,  Craig Conway

Inventor： Neil Feiereisel ,  Craig Conway

IPC: H04J3/06 ,  H04L7/00 ,  H04L25/14

CPC classification number: H04L25/14 ,  H04J3/0682

Abstract: In one embodiment, a system comprises a delay determining unit that may be operable to determine a relative delay between the first signal provided by the first source and the second signal provided by the second source, based upon a travel path of the first signal and a travel path of the second signal. In addition, a delay circuit, comprised within the waveform generator, may be configured to be programmed to delay output of the first signal to output the first signal at a predetermined position with respect to output of the second signal, based on the determined relative delay. More specifically, in one embodiment, the delay circuit may be configured to be automatically programmed to add the relative delay to the output of the first signal to automatically align the output of the first signal with respect to the output of the second signal.

Abstract translation: 在一个实施例中，系统包括延迟确定单元，该延迟确定单元可操作以基于第一信号的行进路径和第一信号的行进路径来确定由第一源提供的第一信号和由第二源提供的第二信号之间的相对延迟 旅行路径的第二个信号。 另外，包括在波形发生器内的延迟电路可以被配置为基于所确定的相对延迟来编程以延迟第一信号的输出，以相对于第二信号的输出在预定位置处输出第一信号 。 更具体地，在一个实施例中，延迟电路可以被配置为被自动编程，以将相对延迟添加到第一信号的输出，以自动对准第一信号的输出相对于第二信号的输出。

公开(公告)号：US20050185621A1

公开(公告)日：2005-08-25

申请号：US11063284

申请日：2005-02-22

Applicant: Raghupathy Sivakumar ,  Hung-Yun Hsieh

Inventor： Raghupathy Sivakumar ,  Hung-Yun Hsieh

IPC: H04B7/216 ,  H04L1/16 ,  H04L1/18 ,  H04L12/56 ,  H04L25/14

CPC classification number: H04L25/14 ,  H04L1/1607 ,  H04L1/1887 ,  H04L45/24 ,  H04L47/27

Abstract: Systems and methods for the communication of data over a plurality of parallel communication paths are provided. Embodiments of the parallel communications systems and methods may discover, characterize, and leverage multiplicity of resources in various network elements to provide network applications with a desired communication objective and level of performance. The systems and methods may dynamically adapt to changes in the network resources to continuously provide the desired communication performance.

Abstract translation: 提供了用于通过多个并行通信路径进行数据通信的系统和方法。 并行通信系统和方法的实施例可以发现，表征和利用各种网络元件中的多个资源，以向网络应用提供期望的通信目标和性能水平。 系统和方法可以动态地适应网络资源的变化，以连续地提供期望的通信性能。

公开(公告)号：US06934866B2

公开(公告)日：2005-08-23

申请号：US10098337

申请日：2002-03-18

Applicant: Jonathan Lin ,  Yong Jiang

Inventor： Jonathan Lin ,  Yong Jiang

IPC: H03L7/00 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/14 ,  G06F1/12

CPC classification number: H03L7/00 ,  H04J3/0697 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/0337 ,  H04L7/0338 ,  H04L25/14

Abstract: A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

公开(公告)号：US06928106B1

公开(公告)日：2005-08-09

申请号：US09557274

申请日：2000-04-24

Applicant: Oscar E. Agazzi

Inventor： Oscar E. Agazzi

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H03H7/30 ,  H03H21/00 ,  H04B1/38 ,  H04B3/23 ,  H04B3/32 ,  H04B3/46 ,  H04L1/00 ,  H04L1/08 ,  H04L1/24 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  H04L29/08

CPC classification number: H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H03H21/0067 ,  H03H2021/007 ,  H03H2021/0074 ,  H04B3/23 ,  H04B3/32 ,  H04B3/487 ,  H04L1/0009 ,  H04L1/0054 ,  H04L1/08 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L69/323 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03681 ,  H04L2025/03745

Abstract: A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

Abstract translation: 一种用于控制多对千兆位收发器的操作的方法。 多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制接收来自串行管理模块的用户定义的输入以及来自DSP和PCS的状态信号和诊断信号​​，并根据用户定义的输入，状态信号和诊断信号​​产生控制信号到DSP和 PCS。

公开(公告)号：US20050152407A1

公开(公告)日：2005-07-14

申请号：US10754204

申请日：2004-01-09

Applicant: Marty Pflum

Inventor： Marty Pflum

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H04L7/00 ,  H04L7/033 ,  H04L25/14 ,  H04J3/06

CPC classification number: H04L25/14 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058 ,  H03K2005/0013 ,  H03K2005/00156 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/033

Abstract: Output clock adjustment for a digital I/O between physical layer devices and media access controller. A method is disclosed for transferring data received on the input of a physical layer device from a transmission medium to an output associated with the physical layer device and to a media independent layer, the transferred data associated with transferred timing information from the physical layer device to the media independent layer. A receive clock is generated and then the data transitions in the received data are synchronized to at least one edge of the receive clock to provide synchronized receive data. The synchronized received data is then transmitted to the media independent layer. The generated receive clock is delayed by a predetermined clock delay to provide a delayed receive clock, and wherein the data transitions in the synchronized receive data is positioned relative to the rising edge of the delayed receive clock at a predetermined position therein following the rising edge thereof. The delayed receive clock transmitting with the transmitted synchronized receive data.

Abstract translation: 物理层设备和媒体访问控制器之间的数字I / O的输出时钟调整。 公开了一种用于将在物理层设备的输入上接收的数据从传输介质传输到与物理层设备相关联的输出和与媒体无关的层的方法，所传送的数据与从物理层设备传输的定时信息相关联， 媒体独立层。 产生接收时钟，然后接收的数据中的数据转换被同步到接收时钟的至少一个边缘以提供同步的接收数据。 然后将同步的接收数据发送到媒体独立层。 产生的接收时钟被延迟预定的时钟延迟以提供延迟的接收时钟，并且其中同步的接收数据中的数据转换相对于延迟的接收时钟在其上升沿之后的预定位置处的上升沿被定位 。 延迟的接收时钟使用发送的同步接收数据进行发送。

公开(公告)号：US20050111604A1

公开(公告)日：2005-05-26

申请号：US10769087

申请日：2004-01-29

Applicant: Ken Okuyama

Inventor： Ken Okuyama

IPC: H04L7/00 ,  H03K19/173 ,  H04L25/14

CPC classification number: H04L25/14

Abstract: Data is serially transferred from an IC1 to an IC2 through a plurality of data transmission paths. Elastic buffers are connected to the plurality of signal paths corresponding the plurality of data transmission paths. A skew adjustment circuit cancels a skew of data strings generated between the plurality of signal paths by a synchronizing process in the elastic buffer. Cancellation of a skew is executed on the basis of a buffer status and a control signal representing process contents in the elastic buffer. A skew generated between the plurality of signal paths of the system having the elastic buffer is canceled.

Abstract translation: 数据通过多个数据传输路径从IC1串行地传送到IC2。 弹性缓冲器连接到对应于多个数据传输路径的多个信号路径。 偏斜调整电路通过弹性缓冲器中的同步处理消除在多个信号路径之间产生的数据串的偏斜。 基于缓冲器状态和表示弹性缓冲器中的处理内容的控制信号执行偏斜的取消。 在具有弹性缓冲器的系统的多个信号路径之间产生的偏斜被消除。