公开(公告)号：US20180358954A1

公开(公告)日：2018-12-13

申请号：US16000582

申请日：2018-06-05

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Jaewook KIM ,  Mino KIM ,  Suhwan KIM ,  Deog-Kyoon JEONG

IPC分类号： H03K3/017 ,  H03K5/06 ,  H03K21/02 ,  H03K5/135 ,  H03K5/26

CPC分类号： H03K3/017 ,  H03K5/06 ,  H03K5/135 ,  H03K5/26 ,  H03K21/02 ,  H03K2005/00156

摘要： In an embodiment, a delay circuit comprises a delay loop controller outputting a signal obtained by operating a start signal and a delayed feedback clock signal output from outside the delay loop controller; and a loop counter configured to determine whether a predetermined delay time has elapsed since the start signal was input according to the delayed feedback clock signal and a predetermined loop count.

公开(公告)号：US09671284B1

公开(公告)日：2017-06-06

申请号：US15407683

申请日：2017-01-17

申请人： KISKEYA MICROSYSTEMS LLC

发明人： Marc Péralte Dandin

IPC分类号： G01J1/44 ,  H03K5/1534 ,  H03K5/00

CPC分类号： G01J1/44 ,  G01J2001/442 ,  G01J2001/4466 ,  H01L31/02027 ,  H03K5/134 ,  H03K5/1534 ,  H03K2005/00026 ,  H03K2005/00156

摘要： A circuit is provided. The circuit includes a single-photon avalanche diode. The circuit further includes a delay element comprising a first regulator and a second regulator, each of which is independently selectable based on a selection signal applied to a selection terminal of the delay element. The delay element is configured to receive, at an inverting section, an event signal indicative of an avalanche event in the single-photon avalanche diode. Furthermore, the delay element is configurable in one of two distinct delay resolution regimes, each corresponding to only one edge of the event signal being actively delayed by the delay element when one of the first regulator and the second regulator is enabled and the other one of the first regulator and the second regulator is turned off.

公开(公告)号：US09015094B2

公开(公告)日：2015-04-21

申请号：US13531226

申请日：2012-06-22

申请人： Manan Suri ,  Barbara De Salvo

发明人： Manan Suri ,  Barbara De Salvo

IPC分类号： G06F15/18 ,  G06J1/00 ,  G06N3/00 ,  G06E1/00 ,  G06E3/00 ,  G06G7/00 ,  G11C11/00 ,  H01L45/00 ,  H03K5/13 ,  H03K5/00

CPC分类号： H01L45/06 ,  G06N3/049 ,  G06N3/0635 ,  H01L45/04 ,  H03K5/13 ,  H03K2005/00026 ,  H03K2005/00156

摘要： A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.

摘要翻译： 延迟发生器包括由基于硫族化物的相变材料制成的至少一个可编程电阻器RPCM，所述电阻器RPCM被初始化，以便产生延迟，使得电阻器RPCM的电阻等于预设值 初始值R0，使得硫族化物处于非晶相，比较器将比较稳定的参考电量与表示可编程电阻器RPCM的电阻的可变电量比较，产生奇点信号s的比较器， 当两个电量之间的差异变化时，产生奇异点。

公开(公告)号：US08766670B2

公开(公告)日：2014-07-01

申请号：US13802903

申请日：2013-03-14

申请人： Leadtrend Technology Corp.

发明人： Ren-Yi Chen ,  Yi-Lun Shen

IPC分类号： G11C7/02

CPC分类号： H03K5/13 ,  H03K2005/00156

摘要： A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0

摘要翻译： 用于产生变压器的可变采样延迟时间的采样和保持电路包括放电检测单元，采样延迟时间生成单元和比较器。 放电检测单元根据第一接通信号和第一参考电流产生第一电压。 第一接通信号的长度随着变压器当前周期的放电时间而变化。 采样延迟时间生成单元根据第一接通信号和第二基准电流产生第二电压。 比较器根据对应于变压器的前一周期的第一电压和对应于变压器当前周期的第二电压，向变压器的控制电路产生采样信号。 第一个参考电流是第二个参考电流的K倍，0

公开(公告)号：US20140043081A1

公开(公告)日：2014-02-13

申请号：US13802903

申请日：2013-03-14

申请人： LEADTREND TECHNOLOGY CORP.

发明人： Ren-Yi Chen ,  Yi-Lun Shen

IPC分类号： H03K5/13

CPC分类号： H03K5/13 ,  H03K2005/00156

摘要： A sample-and-hold circuit for generating a variable sample delay time of a transformer includes a discharge detection unit, a sample delay time generation unit, and a comparator. The discharge detection unit generates a first voltage according to a first turning-on signal and a first reference current. Length of the first turning-on signal is varied with a discharge time of a present period of the transformer. The sample delay time generation unit generates a second voltage according to the first turning-on signal and a second reference current. The comparator generates a sample signal to a control circuit of the transformer according to a first voltage corresponding to a previous period of the transformer and a second voltage corresponding to the present period of the transformer. The first reference current is K times the second reference current, and 0

摘要翻译： 用于产生变压器的可变采样延迟时间的采样和保持电路包括放电检测单元，采样延迟时间生成单元和比较器。 放电检测单元根据第一接通信号和第一参考电流产生第一电压。 第一接通信号的长度随着变压器当前周期的放电时间而变化。 采样延迟时间生成单元根据第一接通信号和第二基准电流产生第二电压。 比较器根据对应于变压器的前一周期的第一电压和对应于变压器当前周期的第二电压，向变压器的控制电路产生采样信号。 第一个参考电流是第二个参考电流的K倍，0

公开(公告)号：US08471546B2

公开(公告)日：2013-06-25

申请号：US12891434

申请日：2010-09-27

申请人： Kouichi Ooga

发明人： Kouichi Ooga

IPC分类号： G05F5/08

CPC分类号： H03K17/284 ,  H03K5/13 ,  H03K2005/00156

摘要： To provide a time constant circuit and the like capable of acquiring a characteristic of an output voltage that attenuates gradually after attenuating steeply, compared to a characteristic that attenuates monotonously. The time constant circuit includes: a series/parallel circuit formed by serially connecting a plurality of parallel circuits each formed with a resistance element and a capacitance element between a first terminal and a second terminal; and a voltage-dividing resistance element connected between a third terminal connected to the second terminal and a fourth terminal. A first parallel circuit is formed with a first resistance element and a first capacitance element, a second parallel circuit with a second resistance element and a second capacitance element, and an n-th parallel circuit with an n-th resistance element and an n-th capacitance element. Note that “n” is the number of the parallel circuits and it is an integer of 2 or larger.

摘要翻译： 为了提供一种时间常数电路等，与能够单调衰减的特性相比，能够获得与陡峭衰减后逐渐衰减的输出电压的特性。 该时间常数电路包括：串联/并联电路，其通过串联连接多个并联电路，每个并联电路各自形成有电阻元件和第一端子与第二端子之间的电容元件; 以及连接在与第二端子连接的第三端子与第四端子之间的分压电阻元件。 第一并联电路形成有第一电阻元件和第一电容元件，具有第二电阻元件的第二并联电路和第二电容元件，以及具有第n电阻元件和第n电容元件的第n并联电路， 电容元件。 注意，“n”是并联电路的数量，它是2或更大的整数。

公开(公告)号：US20120330873A1

公开(公告)日：2012-12-27

申请号：US13531226

申请日：2012-06-22

申请人： Manan SURI ,  Barbara DE SALVO

发明人： Manan SURI ,  Barbara DE SALVO

IPC分类号： H03H11/26 ,  G06N3/04

CPC分类号： H01L45/06 ,  G06N3/049 ,  G06N3/0635 ,  H01L45/04 ,  H03K5/13 ,  H03K2005/00026 ,  H03K2005/00156

摘要： A delay generator comprises at least one programmable resistor RPCM made of a chalcogenide-based phase-change material, said resistor RPCM being initialized, so as to generate a delay, in a way such that the resistance of the resistor RPCM equals a pre-set initial value R0 and such that the chalcogenide is in the amorphous phase, and a comparator comparing a reference electrical quantity that is stable over time with a variable electrical quantity representative of the resistance of the programmable resistor RPCM, the comparator generating a singularity signal s, said singularity being generated when the difference between the two electrical quantities changes sign.

摘要翻译： 延迟发生器包括由基于硫族化物的相变材料制成的至少一个可编程电阻器RPCM，所述电阻器RPCM被初始化，以便产生延迟，使得电阻器RPCM的电阻等于预设值 初始值R0，使得硫族化物处于非晶相，比较器将比较稳定的参考电量与表示可编程电阻器RPCM的电阻的可变电量比较，产生奇点信号s的比较器， 当两个电量之间的差异变化时，产生奇异点。

公开(公告)号：US20120242371A1

公开(公告)日：2012-09-27

申请号：US13356396

申请日：2012-01-23

申请人： Robert Paul Masleid

发明人： Robert Paul Masleid

IPC分类号： H03K19/094

CPC分类号： H03K5/133 ,  H03K5/13 ,  H03K17/005 ,  H03K17/6872 ,  H03K2005/00156 ,  H03K2217/0036

摘要： A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

摘要翻译： 功率高效的多路复用器。 根据第一实施例，功率效率多路复用器包括用于选择性地通过多个输入信号中的一个的传输栅极结构和用于反转多个输入信号中的一个输入信号的堆叠反相器电路。 与传统的多路复用器设计相比，堆叠的反相器和传输门都提供了有益的静态功耗的降低。

公开(公告)号：US07940072B2

公开(公告)日：2011-05-10

申请号：US11989713

申请日：2006-07-28

申请人： Masakatsu Suda

发明人： Masakatsu Suda

IPC分类号： G01R31/26

CPC分类号： G01R31/31922 ,  H03K5/133 ,  H03K2005/00156 ,  H03K2005/00195 ,  H03K2005/00208

摘要： A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.

摘要翻译： 可变延迟电路具有简单的配置，用于并入定时发生器中以实时控制延迟时间并确保定时裕度。 定时发生器的可变延迟电路包括具有多个级联时钟缓冲器的延迟电路; 多个级联数据缓冲器; 以及数据保持电路，用于根据来自延迟电路的时钟向数据缓冲器输出数据。 由数据缓冲器添加到数据的延迟量与由时钟缓冲器添加到时钟的延迟量相同。

公开(公告)号：US07817674B2

公开(公告)日：2010-10-19

申请号：US10754204

申请日：2004-01-09

申请人： Marty Pflum

发明人： Marty Pflum

IPC分类号： H04L7/00

CPC分类号： H04L25/14 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058 ,  H03K2005/0013 ,  H03K2005/00156 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/033

摘要： Output clock adjustment for a digital I/O between physical layer devices and media access controller. A method is disclosed for transferring data received on the input of a physical layer device from a transmission medium to an output associated with the physical layer device and to a media independent layer, the transferred data associated with transferred timing information from the physical layer device to the media independent layer. A receive clock is generated and then the data transitions in the received data are synchronized to at least one edge of the receive clock to provide synchronized receive data. The synchronized received data is then transmitted to the media independent layer. The generated receive clock is delayed by a predetermined clock delay to provide a delayed receive clock, and wherein the data transitions in the synchronized receive data is positioned relative to the rising edge of the delayed receive clock at a predetermined position therein following the rising edge thereof. The delayed receive clock transmitting with the transmitted synchronized receive data.

摘要翻译： 物理层设备和媒体访问控制器之间的数字I / O的输出时钟调整。 公开了一种用于将在物理层设备的输入上接收的数据从传输介质传输到与物理层设备相关联的输出和与媒体无关的层的方法，所传送的数据与从物理层设备传输的定时信息相关联， 媒体独立层。 产生接收时钟，然后接收的数据中的数据转换被同步到接收时钟的至少一个边缘以提供同步的接收数据。 然后将同步的接收数据发送到媒体独立层。 产生的接收时钟被延迟预定的时钟延迟以提供延迟的接收时钟，并且其中同步的接收数据中的数据转换相对于延迟的接收时钟在其上升沿之后的预定位置处的上升沿被定位 。 延迟的接收时钟使用发送的同步接收数据进行发送。