公开(公告)号：US3445926A

公开(公告)日：1969-05-27

申请号：US3445926D

申请日：1967-02-28

Applicant: ELECTRO OPTICAL SYSTEMS INC

Inventor： MEDVED DAVID B ,  GARASI LOUIS A

IPC: H01J37/317 ,  H01L21/00 ,  H01L21/266 ,  H01L7/54 ,  B23K9/00

CPC classification number: H01L21/266 ,  H01J37/3172 ,  H01L21/00 ,  Y10S438/918 ,  Y10S438/945

公开(公告)号：US3392193A

公开(公告)日：1968-07-09

申请号：US41203164

申请日：1964-11-18

Applicant: TEXAS INSTRUMENTS INC

Inventor： HAISTY ROBERT W ,  CRONIN GEORGE R

IPC: H01L29/207

CPC classification number: H01L29/207 ,  Y10S148/056 ,  Y10S148/065 ,  Y10S148/107 ,  Y10S438/918

公开(公告)号：US09431252B2

公开(公告)日：2016-08-30

申请号：US14656847

申请日：2015-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying Zhang

IPC: H01L21/266 ,  H01L29/66 ,  H01L29/739 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/266 ,  H01L21/31138 ,  H01L21/31155 ,  H01L29/66356 ,  H01L29/66477 ,  H01L29/7391 ,  Y10S438/918

Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.

公开(公告)号：US09243345B2

公开(公告)日：2016-01-26

申请号：US14518594

申请日：2014-10-20

Applicant: SUMCO CORPORATION

Inventor： Toshiaki Ono ,  Wataru Ito ,  Jun Fujise

IPC: H01L21/02 ,  C30B33/02 ,  C30B29/06 ,  H01L21/322 ,  H01L21/67 ,  H01L21/687 ,  C30B23/02 ,  C30B25/18 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36

CPC classification number: C30B33/02 ,  C30B23/025 ,  C30B25/186 ,  C30B29/06 ,  H01L21/3225 ,  H01L21/67115 ,  H01L21/68735 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36 ,  Y10S438/918

Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.

Abstract translation: 硅晶片的制造方法提供了可以减少氧沉淀以防止晶片变形产生的硅晶片，并且可以防止由于舟状划痕引起的滑移延伸和作为晶片强度降低的原因的转印划痕， 即使当晶片被提供到快速升温和降落的热处理工艺时。

公开(公告)号：US08890291B2

公开(公告)日：2014-11-18

申请号：US13258962

申请日：2010-03-25

Applicant: Toshiaki Ono ,  Wataru Ito ,  Jun Fujise

Inventor： Toshiaki Ono ,  Wataru Ito ,  Jun Fujise

IPC: H01L21/02 ,  C30B29/06 ,  H01L21/67 ,  H01L21/687 ,  C30B33/02 ,  H01L21/322

CPC classification number: C30B33/02 ,  C30B23/025 ,  C30B25/186 ,  C30B29/06 ,  H01L21/3225 ,  H01L21/67115 ,  H01L21/68735 ,  H01L29/16 ,  H01L29/167 ,  H01L29/36 ,  Y10S438/918

Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.

Abstract translation: 硅晶片的制造方法提供了可以减少氧沉淀以防止晶片变形产生的硅晶片，并且可以防止由于舟状划痕引起的滑移延伸和作为晶片强度降低的原因的转印划痕， 即使当晶片被提供到快速升温和降落的热处理工艺时。

公开(公告)号：US20130224926A1

公开(公告)日：2013-08-29

申请号：US13857578

申请日：2013-04-05

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chai-Hong Jan ,  Mark T. Bohr

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

公开(公告)号：US20110215422A1

公开(公告)日：2011-09-08

申请号：US13107783

申请日：2011-05-13

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L21/8238 ,  H01L29/36 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07507667B2

公开(公告)日：2009-03-24

申请号：US11744446

申请日：2007-05-04

Applicant: Woo Sik Yoo

Inventor： Woo Sik Yoo

IPC: H01L21/44

CPC classification number: H01L21/67115 ,  H01L21/324 ,  H01L21/76254 ,  H01L21/76838 ,  Y10S438/918 ,  Y10S438/967

Abstract: A copper film is treated by applying light at short wavelengths, e.g., at less than 0.6 μm, to heat the copper film and generate a large temperature gradient from the surface of the copper to the interface between the copper and underlying silicon. As a result, grain growth in the copper is enhanced.

Abstract translation: 通过施加短波长例如小于0.6μm的光来处理铜膜，以加热铜膜并产生从铜表面到铜和下硅之间的界面的大的温度梯度。 结果，铜的晶粒生长增强。

公开(公告)号：US07041530B2

公开(公告)日：2006-05-09

申请号：US10864881

申请日：2004-06-10

Applicant: Masahiro Nunoshita ,  Ichiro Yamashita ,  Shigeo Yoshii

Inventor： Masahiro Nunoshita ,  Ichiro Yamashita ,  Shigeo Yoshii

IPC: H01L51/40

CPC classification number: H01L29/127 ,  B82Y10/00 ,  B82Y30/00 ,  C01P2004/64 ,  H01L21/266 ,  H01L29/158 ,  Y10S438/917 ,  Y10S438/918 ,  Y10S438/962

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract translation: 提供了能够控制纳米颗粒的粒度和三维排列的纳米颗粒分散复合材料的制造方法。 制备本发明的纳米颗粒分散复合材料的方法包括：将包含内部包含在蛋白质内的无机材料的多个具有核心细颗粒的核心细颗粒 - 蛋白复合物排列在 衬底的顶表面，去除蛋白质的步骤（b），从衬底的顶表面进行离子注入的步骤（c）和形成纳米颗粒的步骤（d），其包括由离子注入的离子 作为原料植入，在基板的内部。

公开(公告)号：US20050227463A1

公开(公告)日：2005-10-13

申请号：US11097259

申请日：2005-04-04

Applicant: Takayuki Ito ,  Kyoichi Suguro

Inventor： Takayuki Ito ,  Kyoichi Suguro

IPC: H01L21/336 ,  H01L21/425 ,  H01L21/8238

CPC classification number: H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

Abstract: A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

Abstract translation: 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。