公开(公告)号：US08993425B2

公开(公告)日：2015-03-31

申请号：US13718992

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ying Zhang

IPC: H01L21/425 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L21/266 ,  H01L21/31138 ,  H01L21/31155 ,  H01L29/66356 ,  H01L29/66477 ,  H01L29/7391 ,  Y10S438/918

Abstract: An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain.

Abstract translation: 一种实施例集成电路装置及其制造方法。 实施方式包括在由衬底支撑的栅极堆叠上形成第一氮化物层，在与衬底的顶表面形成锐角的方向上在第一氮化物层中注入锗离子，蚀刻掉第一氮化物层的锗注入部分 氮化物层以形成限定在栅极堆叠的第一侧的第一不对称氮化物间隔区，第一非对称氮化物间隔物保护衬底的第一源极/漏极区域免受第一离子注入，以及将离子注入第二源极/漏极区域 的栅极堆叠的第二侧上的衬底，其被第一不对称氮化物间隔物保护以形成第一源极/漏极。

公开(公告)号：US07943468B2

公开(公告)日：2011-05-17

申请号：US12059455

申请日：2008-03-31

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07728347B2

公开(公告)日：2010-06-01

申请号：US12428567

申请日：2009-04-23

Applicant: Akio Ogawa ,  Michihiro Sano ,  Hiroyuki Kato ,  Hiroshi Kotani ,  Tomofumi Yamamuro

Inventor： Akio Ogawa ,  Michihiro Sano ,  Hiroyuki Kato ,  Hiroshi Kotani ,  Tomofumi Yamamuro

IPC: H01L29/24 ,  H01L33/00 ,  H01L21/20 ,  H01L21/36 ,  H01L21/04

CPC classification number: H01L33/285 ,  H01L21/0237 ,  H01L21/02433 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L33/16 ,  Y10S438/914 ,  Y10S438/918

Abstract: A ZnO layer is provided which can obtain emission at a wavelength longer than blue (e.g., 420 nm) and has a novel structure. A transition energy narrower by 0.6 eV or larger than a band gap of ZnO can be obtained by doping S into a ZnO layer.

Abstract translation: 提供了可以获得长于蓝色（例如420nm）的波长的发光并具有新颖结构的ZnO层。 通过将S掺杂到ZnO层中可以获得比ZnO的带隙窄0.6eV或更大的过渡能。

公开(公告)号：US20090242998A1

公开(公告)日：2009-10-01

申请号：US12059455

申请日：2008-03-31

Applicant: Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

Inventor： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

Abstract translation: 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

公开(公告)号：US07501332B2

公开(公告)日：2009-03-10

申请号：US11097259

申请日：2005-04-04

Applicant: Takayuki Ito ,  Kyoichi Suguro

Inventor： Takayuki Ito ,  Kyoichi Suguro

IPC: H01L21/425

CPC classification number: H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

Abstract: A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

Abstract translation: 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

公开(公告)号：US07186631B2

公开(公告)日：2007-03-06

申请号：US11201843

申请日：2005-08-11

Applicant: Seung Woo Jin ,  Min Yong Lee ,  Kyoung Bong Rouh

Inventor： Seung Woo Jin ,  Min Yong Lee ,  Kyoung Bong Rouh

IPC: H01L21/26

CPC classification number: H01L21/28035 ,  H01L21/26513 ,  H01L21/823842 ,  Y10S438/918

Abstract: Provided is a method for manufacturing a semiconductor device comprising forming a device isolation layer on a semiconductor substrate; forming gate insulating layers on the upper part of the semiconductor substrate having the device isolation layers formed thereon; forming an undoped layer for a gate electrode; implanting mixed dopant ions consisting of at least two dopant ions containing 11B ions into the undoped layer, utilizing an ion-implantation mask; and heat-treating the mixed dopant ion-implanted layer.

Abstract translation: 提供一种半导体器件的制造方法，包括在半导体衬底上形成器件隔离层; 在其上形成有器件隔离层的半导体衬底的上部形成栅极绝缘层; 形成用于栅电极的未掺杂层; 使用离子注入掩模将包含至少两种含有11+ B离子的掺杂剂离子组成的混合掺杂剂离子注入到未掺杂的层中; 并对混合掺杂剂离子注入层进行热处理。

公开(公告)号：US20050176229A1

公开(公告)日：2005-08-11

申请号：US10772939

申请日：2004-02-05

Applicant: Liang-Gi Yao ,  Kuen-Chyr Lee ,  Shih-Chang Chen ,  Mong-Song Liang

Inventor： Liang-Gi Yao ,  Kuen-Chyr Lee ,  Shih-Chang Chen ,  Mong-Song Liang

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  Y10S438/918

Abstract: A method of forming an Si—Ge epitaxial layer comprising the following steps. A structure is provided and a doped Si—Ge seed layer is formed thereover. The doped Si—Ge seed layer having increased nucleation sites. A Si—Ge epitaxial layer upon the doped Si—Ge seed layer whereby the Si—Ge epitaxial layer lacks discontinuity.

Abstract translation: 一种形成Si-Ge外延层的方法，包括以下步骤。 提供一种结构，并在其上形成掺杂的Si-Ge种子层。 掺杂的Si-Ge种子层具有增加的成核位点。 在掺杂Si-Ge晶种层上的Si-Ge外延层，由此Si-Ge外延层缺少不连续性。

公开(公告)号：US20040023489A1

公开(公告)日：2004-02-05

申请号：US10210932

申请日：2002-08-02

Inventor： Dinesh Chopra

IPC: H01L021/326 ,  H01L021/479 ,  H01L021/44

CPC classification number: H01L21/76843 ,  H01L21/265 ,  H01L21/76859 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089 ,  Y10S438/918 ,  Y10S438/946

Abstract: The present invention is generally directed to various methods of using ion implantation techniques to control various metal formation processes. In one illustrative embodiment, the method comprises forming a metal seed layer above a patterned layer of insulating material, the patterned layer of insulating material defining a plurality of field areas, deactivating at least a portion of the metal seed layer in areas where the metal seed layer is positioned above at least some of the field areas, and performing a deposition process to deposit a metal layer above the metal seed layer. In some embodiments, the metal may be comprised of copper, platinum, nickel, tantalum, tungsten, cobalt, etc. Portions of the metal seed layer may be deactivated by implanting ions into portions of the metal seed layer positioned above at least some of the field areas. The implanted ions may be comprised of nitrogen, carbon, silicon, hydrogen, etc. In yet another illustrative embodiment, the system comprises a stencil mask implant tool for implanting ions into selected areas of a metal seed layer formed above a patterned layer of insulating material that defines a plurality of field areas, the ions being implanted into areas of the metal seed layer positioned above at least some of the field areas.

公开(公告)号：US06562686B2

公开(公告)日：2003-05-13

申请号：US10083187

申请日：2002-02-26

Applicant: Hi Deok Lee

Inventor： Hi Deok Lee

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S438/918

Abstract: A method for fabricating a semiconductor device employing a salicide (self-aligned silicide) structure is disclosed. The method prevents a junction leakage current from being increased at a portion of a source/drain region which is adjacent to an field oxide, by forming the source/drain region comprised of a relatively deep SID region and a relatively shallow SID region, wherein the deep SID region is formed adjacent to the field oxide and the shallow SID region is formed adjacent to the insulating film spacer. The method comprises the steps of forming a field oxide in a semiconductor substrate, forming a gate oxide and a gate electrode on the semiconductor substrate, forming an LDD region in the semiconductor substrate along a side of the gate electrode, forming a sidewall spacer on each sidewall of the gate electrode, forming a protection layer pattern covering the field oxide and a portion of the LDD region, forming a SEG layer where the protection layer pattern is not covered, removing the protection layer pattern to expose the portion of the LDD region, forming a source/drain region comprised of a deep SID region and a shallow SID region, forming a silicide layer on the gate electrode, the SEG layer and the deep SID region.

Abstract translation: 公开了一种制造采用硅化物（自对准硅化物）结构的半导体器件的方法。 该方法通过形成由相对较深的SID区域和相对较浅的SID区域构成的源极/漏极区域来防止在与场氧化物相邻的源极/漏极区域的部分处增加结漏电流，其中， 形成与场氧化物相邻的深SID区域，并且与绝缘膜间隔物相邻形成浅的SID区域。 该方法包括以下步骤：在半导体衬底中形成场氧化物，在半导体衬底上形成栅极氧化物和栅电极，沿半导体衬底沿着栅电极侧形成LDD区， 形成覆盖场氧化物的保护层图案和LDD区域的一部分，形成保护层图案未被覆盖的SEG层，去除保护层图案以露出LDD区域的部分， 形成由深SID区域和浅SID区域构成的源极/漏极区域，在栅电极，SEG层和深SID区域上形成硅化物层。

公开(公告)号：US20020140029A1

公开(公告)日：2002-10-03

申请号：US10083187

申请日：2002-02-26

Inventor： Hi Deok Lee

IPC: H01L031/113

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S438/918

Abstract: A method for fabricating a semiconductor device employing a salicide (self-aligned silicide) structure is disclosed. The method prevents a junction leakage current from being increased at a portion of a source/drain region which is adjacent to an field oxide, by forming the source/drain region comprised of a relatively deep SID region and a relatively shallow SID region, wherein the deep SID region is formed adjacent to the field oxide and the shallow SID region is formed adjacent to the insulating film spacer. The method comprises the steps of forming a field oxide in a semiconductor substrate, forming a gate oxide and a gate electrode on the semiconductor substrate, forming an LDD region in the semiconductor substrate along a side of the gate electrode, forming a sidewall spacer on each sidewall of the gate electrode, forming a protection layer pattern covering the field oxide and a portion of the LDD region, forming a SEG layer where the protection layer pattern is not covered, removing the protection layer pattern to expose the portion of the LDD region, forming a source/drain region comprised of a deep SID region and a shallow SID region, forming a silicide layer on the gate electrode, the SEG layer and the deep SID region.

Abstract translation: 公开了一种制造采用硅化物（自对准硅化物）结构的半导体器件的方法。 该方法通过形成由相对较深的SID区域和相对较浅的SID区域构成的源极/漏极区域来防止在与场氧化物相邻的源极/漏极区域的部分处增加结漏电流，其中， 形成与场氧化物相邻的深SID区域，并且与绝缘膜间隔物相邻形成浅的SID区域。 该方法包括以下步骤：在半导体衬底中形成场氧化物，在半导体衬底上形成栅极氧化物和栅电极，沿半导体衬底沿着栅电极侧形成LDD区， 形成覆盖场氧化物的保护层图案和LDD区域的一部分，形成保护层图案未被覆盖的SEG层，去除保护层图案以露出LDD区域的一部分， 形成由深SID区域和浅SID区域构成的源极/漏极区域，在栅电极，SEG层和深SID区域上形成硅化物层。