公开(公告)号：US06586306B2

公开(公告)日：2003-07-01

申请号：US10125271

申请日：2002-04-18

Applicant: Hi Deok Lee ,  Seong Hyung Park

Inventor： Hi Deok Lee ,  Seong Hyung Park

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.

公开(公告)号：US06169018A

公开(公告)日：2001-01-02

申请号：US09114290

申请日：1998-07-13

Applicant: Hi-Deok Lee

Inventor： Hi-Deok Lee

IPC: H01L213205

CPC classification number: H01L21/823462

Abstract: The invention relates to a fabrication method of a semiconductor device having dual gates, and more particularly to a fabrication method of dual gates which respectively have a gate insulating film having a different thickness, which includes the steps of providing a semiconductor substrate having a first region and a second region; sequentially forming a first insulating film and an oxidizable film on the first region of the substrate; and forming a second insulating film on the second region of the substrate. Since, when forming the second insulating film, the oxidizable film becomes an oxide film, which oxide film is combined with the first insulating film, thus forming the first gate insulating film, the first gate insulating film is formed thicker than the second gate insulating film in accordance with a simplified oxidation process.

Abstract translation: 本发明涉及具有双栅极的半导体器件的制造方法，更具体地涉及分别具有不同厚度的栅极绝缘膜的双栅极的制造方法，其包括以下步骤：提供具有第一区域的半导体衬底 和第二区域; 在基板的第一区域依次形成第一绝缘膜和可氧化膜; 以及在所述衬底的所述第二区域上形成第二绝缘膜。 由于当形成第二绝缘膜时，可氧化膜成为氧化膜，该氧化膜与第一绝缘膜结合，从而形成第一栅极绝缘膜，第一栅极绝缘膜形成得比第二栅极绝缘膜厚 根据简化的氧化工艺。

公开(公告)号：US5733433A

公开(公告)日：1998-03-31

申请号：US475536

申请日：1995-06-07

Applicant: Ho Jun Lee ,  Hi Deok Lee ,  Jae Duk Lee ,  Jun Bo Yoon ,  Ki Ho Han ,  Jae Kwan Kim ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

Inventor： Ho Jun Lee ,  Hi Deok Lee ,  Jae Duk Lee ,  Jun Bo Yoon ,  Ki Ho Han ,  Jae Kwan Kim ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

IPC: B41J2/05 ,  B41J2/14 ,  B41J2/16 ,  C25F3/14 ,  C25F3/16

CPC classification number: B41J2/14129 ,  B41J2/1603 ,  B41J2/1626 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2202/13

Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

公开(公告)号：US07112529B2

公开(公告)日：2006-09-26

申请号：US10994440

申请日：2004-11-22

Applicant: Sung-hyung Park ,  Hi-Deok Lee

Inventor： Sung-hyung Park ,  Hi-Deok Lee

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed herein is a method of improving residue and thermal characteristics of a semiconductor device. The method comprises the steps of a) depositing nickel and cobalt layers sequentially on a silicone substrate having a transistor formed thereon, b) depositing a capping layer on the cobalt layer, c) forming a silicide layer from the cobalt and nickel layers deposited on the silicone substrate by heat treatment, and d) wet etching to remove a residue. As the silicide layer is formed by additionally deposing the capping layer of titanium nitride on triple layers of silicone, cobalt and nickel, thermal stability for a thermal process performed when forming the silicide is ensured, and as resistance caused by an etchant is eliminated by the subsequent etching process, the residue is completely removed.

Abstract translation: 本文公开了一种改善半导体器件的残余物和热特性的方法。 该方法包括以下步骤：a）将镍和钴层依次沉积在其上形成有晶体管的硅树脂基底上，b）在钴层上沉积覆盖层，c）从沉积在其上的钴和镍层形成硅化物层 通过热处理的有机硅基材，以及d）湿蚀刻以除去残余物。 由于硅化物层通过另外在氮化硅，钴和镍三层上另外去除氮化钛的覆盖层而形成，所以确保了在形成硅化物时进行的热处理的热稳定性，并且由于蚀刻剂引起的电阻消除 随后的蚀刻工艺，残留物被完全除去。

公开(公告)号：US06709939B2

公开(公告)日：2004-03-23

申请号：US10409964

申请日：2003-04-09

Applicant: Hi Deok Lee ,  Seong Hyung Park

Inventor： Hi Deok Lee ,  Seong Hyung Park

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.

Abstract translation: 公开了一种制造半导体器件的方法。 在由自对准硅化物组成的高速装置结构中，为了制造在同一芯片中具有至少两个栅极氧化物结构的器件，形成芯部器件区域的LDD区域，形成LDD区域的离子注入工艺 具有厚栅极氧化物的输入/输出器件区域和用于在具有薄栅极氧化物的芯器件区域的场氧化物的边缘处形成源极/漏极区域的工艺同时进行，从而增加深度 的连接区域。 因此，在外围电路区域的结区域中结漏电流减小，并且处理简化。 结果，改善了设备的工艺成品率和可靠性。

公开(公告)号：US06611030B1

公开(公告)日：2003-08-26

申请号：US09487227

申请日：2000-01-19

Applicant: Hi-deok Lee

Inventor： Hi-deok Lee

IPC: H01L2102

CPC classification number: H01L27/092 ,  H01L21/76898 ,  H01L21/823807 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved semiconductor device, and a corresponding fabrication method thereof, are provided that include a ground region defined in a semiconductor substrate. A hole is formed using a known electropolishing system to electropolish a portion of a bottom surface of the substrate which corresponds to the ground region. A metal layer is formed on the bottom surface of the substrate and in the hole. The metal layer serves as ground by being linked with a ground metal line formed on a substrate surface.

Abstract translation: 提供一种改进的半导体器件及其相应的制造方法，其包括限定在半导体衬底中的接地区域。 使用已知的电解抛光系统形成孔，以电抛光对应于地面区域的衬底的底部表面的一部分。 金属层形成在基板的底面和孔中。 金属层通过与形成在基板表面上的接地金属线连接而用作接地。

公开(公告)号：US5877791A

公开(公告)日：1999-03-02

申请号：US763421

申请日：1996-12-11

Applicant: Ho Jun Lee ,  Hi Deok Lee ,  Jae Duk Lee ,  Jun Bo Yoon ,  Ki Ho Han ,  Jae Kwan Kim ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

Inventor： Ho Jun Lee ,  Hi Deok Lee ,  Jae Duk Lee ,  Jun Bo Yoon ,  Ki Ho Han ,  Jae Kwan Kim ,  Chul Hi Han ,  Choong Ki Kim ,  Doo Won Seo

IPC: B41J2/05 ,  B41J2/14 ,  B41J2/16 ,  B41J2/135 ,  B41J2/145

CPC classification number: B41J2/14129 ,  B41J2/1603 ,  B41J2/1626 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2202/13

Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

Abstract translation: 一种发热型喷墨打印头，包括用于从墨水容器接收墨水的墨水供应通道，用于存储墨水的喷嘴和全部直接形成在基材上的喷嘴，以及用于制造喷墨的方法 使用电解抛光工艺的打印头以及用于制造喷墨打印头的方法。 使用电解抛光工艺制造喷墨打印头，从而实现精确和廉价的制造。

公开(公告)号：US20050227469A1

公开(公告)日：2005-10-13

申请号：US10990922

申请日：2004-11-17

Applicant: Sung-hyung Park ,  Hi-deok Lee

Inventor： Sung-hyung Park ,  Hi-deok Lee

IPC: H01L21/24 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6659 ,  H01L29/7833

Abstract: Disclosed herein is a method of manufacturing a semiconductor device. The method comprises the steps of a) depositing nickel and cobalt layers sequentially on a silicone substrate having a transistor formed thereon, b) forming a silicide layer from the nickel and cobalt layers deposited on the silicone substrate by a rapid thermal process, and c) annealing and wet-etching the semiconductor device obtained in the step b). As the double layers of nickel/cobalt are formed, a resistance difference between N-polysilicone and P-polysilicone is lowered, and thermal stability during a subsequent heat treatment process after forming the silicide is enhanced.

Abstract translation: 本文公开了一种制造半导体器件的方法。 该方法包括以下步骤：a）将镍和钴层依次沉积在其上形成有晶体管的硅树脂衬底上，b）通过快速热处理从沉积在硅氧烷衬底上的镍和钴层形成硅化物层，以及c） 对步骤b）中获得的半导体器件进行退火和湿蚀刻。 当形成双层镍/钴时，N-聚硅氧烷和P-聚硅氧烷之间的电阻差降低，并且在形成硅化物之后的后续热处理工艺中的热稳定性增强。

公开(公告)号：US06562686B2

公开(公告)日：2003-05-13

申请号：US10083187

申请日：2002-02-26

Applicant: Hi Deok Lee

Inventor： Hi Deok Lee

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S438/918

Abstract: A method for fabricating a semiconductor device employing a salicide (self-aligned silicide) structure is disclosed. The method prevents a junction leakage current from being increased at a portion of a source/drain region which is adjacent to an field oxide, by forming the source/drain region comprised of a relatively deep SID region and a relatively shallow SID region, wherein the deep SID region is formed adjacent to the field oxide and the shallow SID region is formed adjacent to the insulating film spacer. The method comprises the steps of forming a field oxide in a semiconductor substrate, forming a gate oxide and a gate electrode on the semiconductor substrate, forming an LDD region in the semiconductor substrate along a side of the gate electrode, forming a sidewall spacer on each sidewall of the gate electrode, forming a protection layer pattern covering the field oxide and a portion of the LDD region, forming a SEG layer where the protection layer pattern is not covered, removing the protection layer pattern to expose the portion of the LDD region, forming a source/drain region comprised of a deep SID region and a shallow SID region, forming a silicide layer on the gate electrode, the SEG layer and the deep SID region.

Abstract translation: 公开了一种制造采用硅化物（自对准硅化物）结构的半导体器件的方法。 该方法通过形成由相对较深的SID区域和相对较浅的SID区域构成的源极/漏极区域来防止在与场氧化物相邻的源极/漏极区域的部分处增加结漏电流，其中， 形成与场氧化物相邻的深SID区域，并且与绝缘膜间隔物相邻形成浅的SID区域。 该方法包括以下步骤：在半导体衬底中形成场氧化物，在半导体衬底上形成栅极氧化物和栅电极，沿半导体衬底沿着栅电极侧形成LDD区， 形成覆盖场氧化物的保护层图案和LDD区域的一部分，形成保护层图案未被覆盖的SEG层，去除保护层图案以露出LDD区域的部分， 形成由深SID区域和浅SID区域构成的源极/漏极区域，在栅电极，SEG层和深SID区域上形成硅化物层。

公开(公告)号：US06548870B1

公开(公告)日：2003-04-15

申请号：US09723222

申请日：2000-11-28

Applicant: Hi Deok Lee

Inventor： Hi Deok Lee

IPC: H01L2976

CPC classification number: H01L29/42372 ,  H01L21/82345 ,  H01L29/66484 ,  H01L29/7831

Abstract: In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity region and the second impurity region. At least two gate electrodes are formed on the gate insulating layer, and are insulated from one another by an intergate insulation layer.

Abstract translation: 在半导体器件中，在半导体衬底的表面中以规则的间隔形成第一杂质区和第二杂质区，并且在半导体衬底上在第一杂质区和第二杂质区之间形成栅极绝缘层。 在栅极绝缘层上形成至少两个栅电极，并通过栅间绝缘层彼此绝缘。