公开(公告)号：US20090187010A1

公开(公告)日：2009-07-23

申请号：US12320556

申请日：2009-01-29

Applicant: Shigeo Yoshii ,  Kazuaki Nishio ,  Shinya Kumagai ,  Ichiro Yamashita

Inventor： Shigeo Yoshii ,  Kazuaki Nishio ,  Shinya Kumagai ,  Ichiro Yamashita

IPC: C07K17/00

CPC classification number: C07K14/47 ,  B82B1/00 ,  B82Y30/00

Abstract: To provide a method of arranging ferritin by which a high rate of the number of the molecular film spots on which sole ferritin molecule was arranged in effect, with respect to total number of the molecular film spots provided for arranging ferritin (sole arrangement rate) is achieved is objected to. Specifically, in Fer8 ferritin having a sequence excluding 7 amino acids of from the second to the eighth, from an amino acid sequence (Fer0 sequence) translated from a naturally occurring DNA sequence, lysine at position 91 is substituted with glutamic acid.

Abstract translation: 为了提供一种安排铁蛋白的方法，相对于提供用于安排铁蛋白的总分子膜点数（单独排列速率），通过该铁蛋白排列高分子膜斑点的数量，单个铁蛋白分子排列有效的方法是： 实现是反对的。 具体而言，在来自第二至第八的7个氨基酸序列的Fer8铁蛋白中，从天然存在的DNA序列翻译的氨基酸序列（Fer0序列）中，91位的赖氨酸被谷氨酸取代。

公开(公告)号：US07419529B2

公开(公告)日：2008-09-02

申请号：US11284910

申请日：2005-11-23

Applicant: Shigeo Yoshii ,  Michihito Ueda ,  Nozomu Matsukawa ,  Ichiro Yamashita

Inventor： Shigeo Yoshii ,  Michihito Ueda ,  Nozomu Matsukawa ,  Ichiro Yamashita

IPC: B22F9/20

CPC classification number: B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332

Abstract: An object of the present invention is to provide a method of forming fine particles on a substrate in which reoxidization of reduced fine particles is suppressed. Reduced fine particles (FeO fine particles) are formed by embedding metal oxide fine particles (Fe2O3 fine particles) fixed on a p type silicon semiconductor substrate into a silicon oxidized film, and carrying out a heat treatment in a reducing gas atmosphere. Presence of the silicon oxidized film enables suppression of reoxidization of the reduced fine particles (FeO fine particles) due to exposure to the ambient air.

Abstract translation: 本发明的目的是提供一种在抑制还原的微粒的再氧化的基板上形成微粒的方法。 通过将固定在p型硅半导体衬底上的金属氧化物微粒（Fe 2 O 3 O 3微粒）嵌入到硅氧化膜中而形成还原的微粒（FeO微粒） ，并在还原气体气氛中进行热处理。 硅氧化膜的存在能够抑制由于暴露于环境空气而导致的还原的微粒（FeO微粒）的再氧化。

公开(公告)号：US6087725A

公开(公告)日：2000-07-11

申请号：US161498

申请日：1998-09-28

Applicant: Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

Inventor： Shigeo Yoshii ,  Yoichi Sasai ,  Satoshi Kamiyama ,  Tohru Saitoh ,  Takashi Nishikawa ,  Ryoko Miyanaga

IPC: H01L33/28 ,  H01L33/40 ,  H01L33/00

CPC classification number: H01L33/40 ,  H01L33/28

Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.

Abstract translation: 在n型GaAs的衬底上，n型Zn0.9Mg0.1S0.13Se0.87的n型覆层，n型ZnS0.06Se0.94的n型导光层，n型ZnS0.06Se0.94的有源层 ZnCdSe和p型ZnS0.06Se0.94的p型导光层依次形成。 在p型导光层上形成p型接触结构。 p型接触结构包括第一层p型ZnS0.31Se0.54Te0.15，第二层ZnS0.47Se0.28Te0.25，第三层p型ZnS0.65Te0.35，第四层 的p型ZnS0.5Te0.5和第五层p型ZnTe。

公开(公告)号：US07919596B2

公开(公告)日：2011-04-05

申请号：US12320556

申请日：2009-01-29

Applicant: Shigeo Yoshii ,  Kazuaki Nishio ,  Shinya Kumagai ,  Ichiro Yamashita

Inventor： Shigeo Yoshii ,  Kazuaki Nishio ,  Shinya Kumagai ,  Ichiro Yamashita

IPC: C07K14/00 ,  H01L21/00 ,  H01L21/314 ,  H01L21/471

CPC classification number: C07K14/47 ,  B82B1/00 ,  B82Y30/00

Abstract: To provide a method of arranging ferritin by which a high rate of the number of the molecular film spots on which sole ferritin molecule was arranged in effect, with respect to total number of the molecular film spots provided for arranging ferritin (sole arrangement rate) is achieved is objected to. Specifically, in Fer8 ferritin having a sequence excluding 7 amino acids of from the second to the eighth, from an amino acid sequence (Fer0 sequence) translated from a naturally occurring DNA sequence, lysine at position 91 is substituted with glutamic acid.

Abstract translation: 为了提供一种安排铁蛋白的方法，相对于提供用于安排铁蛋白的总分子膜点数（单独排列速率），通过该铁蛋白排列高分子膜斑点的数量，单个铁蛋白分子排列有效的方法是： 实现是反对的。 具体而言，在来自第二至第八的7个氨基酸序列的Fer8铁蛋白中，从天然存在的DNA序列翻译的氨基酸序列（Fer0序列）中，91位的赖氨酸被谷氨酸取代。

公开(公告)号：US07419849B2

公开(公告)日：2008-09-02

申请号：US11878691

申请日：2007-07-26

Applicant: Shinya Kumagai ,  Shigeo Yoshii ,  Nozomu Matsukawa ,  Ichiro Yamashita

Inventor： Shinya Kumagai ,  Shigeo Yoshii ,  Nozomu Matsukawa ,  Ichiro Yamashita

IPC: H01L51/40

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  H01L49/006 ,  Y10S438/962 ,  Y10S977/773

Abstract: The present invention provides a method for production of a single electron semiconductor element (SET) in which a quantum dot is selectively arranged in a nano gap between fine electrodes, whereby the product yield is significantly improved, leading to excellent practical applicability. The method for production of SET of the present invention is characterized in that a solution containing ferritin including a metal or semiconductor particle therein, and a nonionic surfactant is dropped on a substrate having a source electrode and a drain electrode formed by laminating a titanium film and a film of a metal other than titanium, whereby the ferritin is selectively arranged in a nano gap between the source electrode/drain electrode.

Abstract translation: 本发明提供一种单电子半导体元件（SET）的制造方法，其中量子点选择性地排列在细电极之间的纳米间隙中，从而显着提高了产品产率，从而实现了优异的实用性。 本发明的SET的制造方法的特征在于，将含有金属或半导体粒子的铁蛋白和非离子表面活性剂的溶液滴落在具有源极电极和漏电极的基板上，所述源极和漏极通过层叠钛膜和 除钛以外的金属的膜，由此铁素体选择性地排列在源电极/漏电极之间的纳米间隙中。

公开(公告)号：US20050067615A1

公开(公告)日：2005-03-31

申请号：US10962492

申请日：2004-10-13

Applicant: Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

Inventor： Shigeo Yoshii ,  Nobuyuki Otsuka ,  Koichi Mizuno ,  Asamira Suzuki

IPC: H01L29/68 ,  H01L29/06 ,  H01L29/08 ,  H01L29/12 ,  H01L29/737 ,  H01L31/0328

CPC classification number: B82Y10/00 ,  H01L29/0817 ,  H01L29/127 ,  H01L29/7371

Abstract: The present invention relates to a semiconductor device comprising a substrate (101); a semiconductor multi-layered structure formed on the substrate (101); the semiconductor multi-layered structure comprising an emitter layer (102), a base layer (105), and a collector layer (107), each composed of a group III-V n-type compound semiconductor and layered in this order; a quantum dot barrier layer (103) disposed between the emitter layer (102) and the base layer (105); a collector electrode (110), a base electrode (111) and an emitter electrode (112) connected to the collector layer (107), the base layer (105) and the emitter layer (102), respectively; the quantum dot barrier layer (103) comprising a plurality of quantum dots (103c); the quantum dots (103) being sandwiched between first and second barrier layers (103a, 103d) from the emitter layer side and the base layer side, respectively; each of the quantum dots (103c) having a convex portion that is convex to the base layer (105); a base layer (105) side interface (d1) in the second barrier layer (103d), and collector layer side and emitter layer side interfaces (d2, d3) in the base layer (105); the interfaces having curvatures (d12, d22, d23) that are convex to the collector layer (107) corresponding to the convex portions of the quantum dots (103c).

Abstract translation: 本发明涉及一种包括衬底（101）的半导体器件; 形成在所述基板（101）上的半导体多层结构; 所述半导体多层结构包括由III-V族N型化合物半导体构成的发射极层（102），基极层（105）和集电极层（107），并且按顺序层叠; 设置在发射极层（102）和基极层（105）之间的量子点势垒层（103）; 分别与集电极层（107）连接的集电极（110），基极（111）和发射极（112），基极层（105）和发射极层（102） 所述量子点势垒层（103）包括多个量子点（103c）; 量子点（103）分别从发射极侧和基极侧夹在第一和第二阻挡层（103a，103d）之间; 每个量子点（103c）具有与基底层（105）凸起的凸部; 第二阻挡层（103d）中的基底层（105）侧界面（d1），以及基底层（105）中的集电极层侧和发射极层侧界面（d2，d3） 具有对应于量子点（103c）的凸部的与集电体层（107）凸起的曲率（d12，d22，d23）的界面。

公开(公告)号：US20050042386A1

公开(公告)日：2005-02-24

申请号：US10864881

申请日：2004-06-10

Applicant: Masahiro Nunoshita ,  Ichiro Yamashita ,  Shigeo Yoshii

Inventor： Masahiro Nunoshita ,  Ichiro Yamashita ,  Shigeo Yoshii

IPC: B05D3/02 ,  H01L21/266 ,  H01L29/12 ,  H01L29/15

CPC classification number: H01L29/127 ,  B82Y10/00 ,  B82Y30/00 ,  C01P2004/64 ,  H01L21/266 ,  H01L29/158 ,  Y10S438/917 ,  Y10S438/918 ,  Y10S438/962

Abstract: A method of the production of a nanoparticle dispersed composite material capable of controlling a particle size and a three dimensional arrangement of the nanoparticles is provided. The method of the production of a nanoparticle dispersed composite material of the present invention includes a step (a) of arranging a plurality of core fine particle-protein complexes having a core fine particle, which comprises an inorganic material, internally included within a protein on the top surface of a substrate, a step (b) of removing the protein, a step (c) of conducting ion implantation from the top surface of the substrate, and a step (d) of forming nanoparticles including the ion implanted by the ion implantation as a raw material, inside of the substrate.

Abstract translation: 提供了能够控制纳米颗粒的粒度和三维排列的纳米颗粒分散复合材料的制造方法。 制备本发明的纳米颗粒分散复合材料的方法包括：将包含内部包含在蛋白质内的无机材料的多个具有核心细颗粒的核心细颗粒 - 蛋白复合物排列在 衬底的顶表面，去除蛋白质的步骤（b），从衬底的顶表面进行离子注入的步骤（c）和形成纳米颗粒的步骤（d），其包括由离子注入的离子 作为原料植入，在基板的内部。

公开(公告)号：US06740928B2

公开(公告)日：2004-05-25

申请号：US10350140

申请日：2003-01-24

Applicant: Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

Inventor： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

IPC: H01L29788

CPC classification number: B82Y10/00 ,  G11C13/02 ,  G11C13/025 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7883

Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.

Abstract translation: 本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。 电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷 保持在电荷保持颗粒中。

公开(公告)号：US06548825B1

公开(公告)日：2003-04-15

申请号：US09587268

申请日：2000-06-05

Applicant: Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

Inventor： Shigeo Yoshii ,  Kiyoshi Morimoto ,  Kiyoyuki Morita ,  Haruyuki Sorada

IPC: H01L310328

CPC classification number: B82Y10/00 ,  G11C13/02 ,  G11C13/025 ,  G11C16/0408 ,  G11C16/0466 ,  G11C2216/06 ,  H01L29/42332 ,  H01L29/7883

Abstract: The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.

Abstract translation: 本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。 电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷 保持在电荷保持颗粒中。

公开(公告)号：US5822347A

公开(公告)日：1998-10-13

申请号：US589488

申请日：1996-01-22

Applicant: Toshiya Yokogawa ,  Shigeo Yoshii ,  Yoichi Sasai

Inventor： Toshiya Yokogawa ,  Shigeo Yoshii ,  Yoichi Sasai

IPC: H01L33/00 ,  H01L33/10 ,  H01L33/28 ,  H01L33/46 ,  H01S5/183 ,  H01S5/20 ,  H01S5/22 ,  H01S5/223 ,  H01S5/327 ,  H01S5/347 ,  H01S3/19 ,  H01L29/22

CPC classification number: H01L33/28 ,  B82Y20/00 ,  H01L33/0083 ,  H01L33/0087 ,  H01L33/465 ,  H01S5/18341 ,  H01S5/327 ,  H01S5/347 ,  H01L33/105 ,  H01S2301/166 ,  H01S5/0207 ,  H01S5/02461 ,  H01S5/18308 ,  H01S5/18369 ,  H01S5/2063 ,  H01S5/2081 ,  H01S5/2211 ,  H01S5/2214 ,  H01S5/2231

Abstract: In a II-VI group semiconductor laser, on an n type GaAs substrate, an n type ZnSe layer, a multiquantum well layer of a ZnCdSe well layer and a ZnSe barrier layer, and a p type ZnSe layer are deposited in this order. A polycrystalline ZnO layer is provided on both sides of the p type ZnSe layer for constricting current. Multifilm reflecting mirrors, respectively constituted with a polycrystalline SiO.sub.2 layer and a polycrystalline TiO.sub.2 layer, for obtaining laser oscillation are provided on the p type ZnSe layer as well as on a surface of the n type ZnSe layer exposed by etching the GaAs substrate. Furthermore, a p type AuPd electrode and an n type AuGeNi electrode are respectively provided. Alternatively, on an n type GaAs substrate, an n type ZnSe epitaxial layer, an n type ZnMgSSe cladding layer, an n type ZnSSe optical waveguide layer, a ZnCdSe active layer, a p type ZnSSe optical waveguide layer, a p type ZnMgSSe cladding layer, a p type ZnTe contact layer and a polycrystalline ZnO burying layer are respectively formed. Furthermore, a p type AuPd electrode and an n type In electrode are respectively provided.

Abstract translation: 在II-VI族半导体激光器中，在n型GaAs衬底上依次沉积n型ZnSe层，ZnCdSe阱层的多量子阱层和ZnSe阻挡层以及p型ZnSe层。 在p型ZnSe层的两侧设置多晶ZnO层，用于收缩电流。 在p型ZnSe层以及通过蚀刻GaAs衬底暴露的n型ZnSe层的表面上，设置分别由用于获得激光振荡的多晶SiO 2层和多晶TiO 2层构成的多片反射镜。 此外，分别设置p型AuPd电极和n型AuGeNi电极。 或者，在n型GaAs衬底上，n型ZnSe外延层，n型ZnMgSSe覆层，n型ZnSSe光波导层，ZnCdSe有源层，ap型ZnSSe光波导层，ap型ZnMgSSe覆层，ap 分别形成ZnTe接触层和多晶ZnO掩埋层。 此外，分别设置p型AuPd电极和n型In电极。