公开(公告)号：US20150263070A1

公开(公告)日：2015-09-17

申请号：US14320449

申请日：2014-06-30

Applicant: SK HYNIX INC.

Inventor： Dong-Hyeon LEE ,  Yun-Sun CHOI

IPC: H01L27/24 ,  H01L43/08 ,  G06F12/08 ,  H01L45/00 ,  H01L27/115 ,  H01L43/02 ,  H01L27/22

CPC classification number: H01L27/2463 ,  G06F12/0846 ,  G06F12/0893 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first pillar electrodes spaced apart from each other, a plurality of second pillar electrodes spaced apart from each other, each second pillar electrode being spaced apart from adjacent first pillar electrodes, and a plurality of variable resistance layers enclosing sidewalls of corresponding second pillar electrodes, respectively, wherein a group of adjacent first pillar electrodes is in contact with one variable resistance layer, and a group of adjacent variable resistance layers is in contact with one first pillar electrode.

Abstract translation: 电子设备包括半导体存储器。 半导体存储器包括彼此间隔开的多个第一柱状电极，彼此间​​隔开的多个第二柱状电极，每个第二柱状电极与相邻的第一柱状电极间隔开，以及包围侧壁的多个可变电阻层 分别相邻的第二柱状电极与一个可变电阻层接触，一组相邻的可变电阻层与一个第一柱状电极接触。

公开(公告)号：US09136474B2

公开(公告)日：2015-09-15

申请号：US13867378

申请日：2013-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Nam Hwang

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1666 ,  H01L27/2436 ,  H01L45/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked. After the insulating patterns are formed, metal-semiconductor compounds are formed on the exposed semiconductor patterns.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成半导体图案，使得侧面被下层间绝缘层包围。 形成覆盖半导体图案和下层间绝缘层的下绝缘层。 形成穿过下绝缘层和下层间绝缘层并与半导体图案间隔开的接触结构。 接触结构的上表面高于半导体图案。 形成覆盖接触结构和下绝缘层的上绝缘层。 上绝缘层和下绝缘层形成暴露半导体图案并覆盖接触结构的绝缘图案，并且每个绝缘图案包括依次层叠的下绝缘图案和上绝缘图案。 在形成绝缘图案之后，在暴露的半导体图案上形成金属 - 半导体化合物。

公开(公告)号：US09136306B2

公开(公告)日：2015-09-15

申请号：US13340375

申请日：2011-12-29

Applicant: D. V. Nirmal Ramaswamy ,  Mark S. Korber

Inventor： D. V. Nirmal Ramaswamy ,  Mark S. Korber

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2418 ,  H01L29/456 ,  H01L29/861 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666 ,  H01L45/1683

Abstract: Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

Abstract translation: 一些实施例包括在存储器单元上具有二极管的存储器结构。 存储单元可以包括一对电极之间的可编程材料，可编程材料直接与高k电介质一起包含多价金属氧化物。 二极管可以包括直接在一个存储单元电极上并与存储单元电极电耦合的第一二极管电极，并且可以包括在第一二极管电极的横向外部并且不直接在存储单元上方的第二二极管电极。 一些实施例包括包括存储器结构的存储器阵列，并且一些实施例包括制造存储器结构的方法。

公开(公告)号：US20150255337A1

公开(公告)日：2015-09-10

申请号：US14717387

申请日：2015-05-20

Applicant: International Business Machines Corporation

Inventor： QINGHUANG LIN ,  DIRK PFEIFFER

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5329 ,  H01L28/90 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1683 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device includes an interlevel dielectric layer formed over a substrate and has a first set of openings and a second set of openings formed through the interlevel dielectric layer. The substrate includes conductive areas. A conductive contact structure is formed in the first set of openings in the interlevel dielectric layer to make electrical contact with the conductive areas of the substrate. A functional component is formed in the second set of openings in the interlevel dielectric layer and occupies a same level as the conductive contact structure.

Abstract translation: 电子器件包括形成在衬底上并具有第一组开口的层间电介质层和通过层间介电层形成的第二组开口。 基板包括导电区域。 导电接触结构形成在层间电介质层中的第一组开口中，以与衬底的导电区电接触。 功能部件形成在层间电介质层的第二组开口中，并且与导电接触结构相同。

公开(公告)号：US09118010B2

公开(公告)日：2015-08-25

申请号：US14328056

申请日：2014-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghyun Hong ,  Jaekyu Lee ,  Yong Kwan Kim

IPC: H01L45/00 ,  H01L27/10 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/1683 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1608 ,  H01L45/1675

Abstract: According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top of the first sub lower electrode. The lower electrode includes an upward-tapered shape.

Abstract translation: 根据示例性实施例，可变电阻存储器件包括下电极，其包括间隔物形的第一副下电极和覆盖第一副下电极的弯曲侧壁的第二副下电极。 第二副下电极向上延伸以突出在第一子下电极的顶部之上。 下电极包括向上锥形的形状。

公开(公告)号：US09105840B2

公开(公告)日：2015-08-11

申请号：US14199915

申请日：2014-03-06

Applicant: SK HYNIX INC.

Inventor： Jong-Chul Lee ,  Ja-Chun Ku ,  Sung-Kyu Min ,  Byung-Jick Cho ,  Seung-Beom Baek ,  Hyo-June Kim ,  Won-Ki Ju ,  Hyun-Kyu Kim

IPC: G11C11/34 ,  H01L45/00 ,  H01L43/02 ,  G11C13/00

CPC classification number: H01L45/122 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/71 ,  H01L27/2472 ,  H01L27/249 ,  H01L43/02 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/165 ,  H01L45/1683

Abstract: According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern.

Abstract translation: 根据实施例，半导体存储器可以包括：设置在衬底上并沿第一方向延伸的可变电阻图案; 第一和第二结构包括多个层间电介质层和多个导电层，其交替地层叠在衬底上，并分别与可变电阻图案的一个侧表面和另一个侧表面接触，其中第一堆叠结构具有 沿第一方向延伸的线状，第二层叠结构具有柱状; 以及与第二堆叠结构的一个侧表面接触的柱状导电图案，其不与可变电阻图案接触。

公开(公告)号：US20150206585A1

公开(公告)日：2015-07-23

申请号：US14321719

申请日：2014-07-01

Applicant: SK HYNIX INC.

Inventor： Hyo-Jin KIM

IPC: G11C14/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C11/22 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/73 ,  G11C2213/76 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a first electrode, a second electrode crossing the first electrode, and a variable resistance pattern positioned in an intersection region of the first electrode and the second electrode and buried in the first electrode.

Abstract translation: 提供了包括半导体存储器的电子设备。 半导体存储器包括第一电极，与第一电极交叉的第二电极和位于第一电极和第二电极的交叉区域中并被埋置在第一电极中的可变电阻图案。

公开(公告)号：US09087989B2

公开(公告)日：2015-07-21

申请号：US14069043

申请日：2013-10-31

Applicant: Micron Technology, Inc

Inventor： John A Smythe, III ,  Gurtej S Sandhu

IPC: G11C11/34 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/165 ,  G11C13/0007 ,  G11C2213/56 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1641 ,  H01L45/1683

Abstract: The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

Abstract translation: 本公开包括GCIB处理的电阻性装置，利用GCIB处理的电阻性装置（例如，作为开关，存储器单元）的装置以及用于形成经GCIB处理的电阻装置的方法。 形成GCIB处理的电阻性器件的一种方法包括形成下电极，并在下电极上形成氧化物材料。 氧化物材料暴露于气体簇离子束（GCIB），直到氧化物材料的第一部分的电阻相对于氧化物材料的第二部分的电阻发生变化。 上电极形成在第一部分上。

公开(公告)号：US20150194356A1

公开(公告)日：2015-07-09

申请号：US14665889

申请日：2015-03-23

Applicant: Kun Xu ,  Feng Liu ,  Dominic J. Benvegnu ,  Boguslaw A. Swedek ,  Yuchun Wang ,  Wen-Chiang Tu ,  Laksh Karuppiah

Inventor： Kun Xu ,  Feng Liu ,  Dominic J. Benvegnu ,  Boguslaw A. Swedek ,  Yuchun Wang ,  Wen-Chiang Tu ,  Laksh Karuppiah

IPC: H01L21/66 ,  H01L21/306

CPC classification number: H01L22/26 ,  B24B37/005 ,  B24B37/013 ,  B24B49/12 ,  C01G9/00 ,  G01B11/0625 ,  G01B11/0683 ,  H01L21/30625 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

Abstract: During polishing of a first substrate at a first polishing station, a sequence of measurements by a first in-situ monitoring system is monitored to determining a first time at which the first sequence exhibits a first predefined feature indicating a predetermined thickness of an overlying layer, and during polishing of the first substrate at a second polishing station, a sequence of measurements by a second in-situ monitoring system is monitored to determine a second time indicating clearance of the overlying layer and exposure of the underlying layer. The first time is used to calculate a first adjusted polishing pressure for a second substrate at the first polishing station, and the second time is used to calculate a second adjusted polishing pressure for the second substrate at the second polishing station.

Abstract translation: 在第一抛光站抛光第一衬底期间，监测由第一原位监测系统进行的测量序列，以确定第一次序列呈现指示上覆层的预定厚度的第一预定义特征的第一时间， 并且在第二抛光站抛光第一基板期间，监测由第二原位监测系统进行的测量序列，以确定第二次指示上覆层的间隙和下层的曝光。 第一次用于计算在第一抛光站处的第二基板的第一调整抛光压力，并且第二次用于计算在第二抛光站处的第二基板的第二调整抛光压力。

公开(公告)号：US09076519B2

公开(公告)日：2015-07-07

申请号：US13563233

申请日：2012-07-31

Applicant: Cheong Min Hong ,  Feng Zhou

Inventor： Cheong Min Hong ,  Feng Zhou

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1683

Abstract: A resistive random access memory (ReRAM) device can comprise a first metal layer and a first metal-oxide layer on the first metal layer. The first metal-oxide layer comprises the first metal. A second metal layer can comprise a second metal over and in physical contact with the first metal-oxide layer. A first continuous non-conductive barrier layer can be in physical contact with sidewalls of the first metal layer and sidewalls of the first metal-oxide layer. A second metal-oxide layer can be on the second metal layer. The second metal-oxide layer can comprise the second metal layer. A third metal layer can be over and in physical contact with the second metal-oxide layer. The first and second metal-oxide layers, are further characterized as independent storage mediums.

Abstract translation: 电阻随机存取存储器（ReRAM）器件可以包括在第一金属层上的第一金属层和第一金属氧化物层。 第一金属氧化物层包括第一金属。 第二金属层可以包括与第一金属氧化物层物理接触的第二金属。 第一连续的非导电阻挡层可以与第一金属层的侧壁和第一金属氧化物层的侧壁物理接触。 第二金属氧化物层可以在第二金属层上。 第二金属氧化物层可以包括第二金属层。 第三金属层可以与第二金属氧化物层结合并物理接触。 第一和第二金属氧化物层进一步被表征为独立的存储介质。