公开(公告)号：US20180269223A1

公开(公告)日：2018-09-20

申请号：US15695892

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kazunori HORIGUCHI ,  Takashi OHASHI

IPC: H01L27/11582 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31116 ,  H01L22/12 ,  H01L22/20 ,  H01L27/1157

Abstract: A manufacturing method of a semiconductor memory device includes disposing a first stacked body on a substrate, forming a first through via hole in the first stacked body, and determining to remove an upper portion of the first stacked body based on a comparison of a determined value of a width of the first through via hole with a reference value. The method further includes forming a second film in the first through via hole responsive to the determination to remove the upper portion of the first stacked body, removing the upper portion of the first stacked body and a portion of the second film, and disposing a second stacked body on the first stacked body and the second film. The method further includes forming a second through via hole to expose at least a portion of the second film, and removing the second film in the first through via hole.

公开(公告)号：US20180269219A1

公开(公告)日：2018-09-20

申请号：US15788869

申请日：2017-10-20

Applicant: Toshiba Memory Corporation

Inventor： Sachiyo Ito ,  Ai Omodaka ,  Tatsuhiro Oda

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11575

CPC classification number: H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a circuit portion, a stacked body, at least one columnar member, a device isolation portion, and at least one first support member. The columnar member is in contact with an interconnect layer, and includes a contact extending in a stacking direction of a plurality of electrode films in the stacked body. The device isolation portion is provided in the stacked body and extends in a first direction and the stacking direction. The first support member is provided in the stacked body, extends in the stacking direction, and is located on the device isolation portion in a second direction crossing the first direction and along the upper surface of the substrate.

公开(公告)号：US10079203B2

公开(公告)日：2018-09-18

申请号：US15271605

申请日：2016-09-21

Applicant: Yong-Hoon Son ,  Cha-Dong Yeo ,  Han-Mei Choi ,  Kyung-Hyun Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

Inventor： Yong-Hoon Son ,  Cha-Dong Yeo ,  Han-Mei Choi ,  Kyung-Hyun Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC: H01L23/522 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/1157

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

公开(公告)号：US20180261687A1

公开(公告)日：2018-09-13

申请号：US15919375

申请日：2018-03-13

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Panpan LIU ,  Haiyang ZHANG

IPC: H01L29/66 ,  H01L21/822 ,  H01L21/02 ,  H01L27/06 ,  H01L27/12 ,  H01L27/11524 ,  G11C16/04

CPC classification number: H01L29/66787 ,  G11C16/0483 ,  H01L21/02244 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/1211

Abstract: A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.

公开(公告)号：US20180261608A1

公开(公告)日：2018-09-13

申请号：US15917160

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Osamu MATSUURA ,  Satoshi TATARA

IPC: H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory device includes a stacked body, a semiconductor member, and a first insulating member. Electrode films and insulating films are alternately stacked along a first direction in the stacked body. An end part of the stacked body is shaped like a staircase in which a terrace is formed for each of the electrode films. A portion of the electrode film placed in the end part is thicker than a portion of the electrode film placed in a central part of the stacked body. The semiconductor member extends in the first direction and penetrates through the central part of the stacked body. The first insulating member extends in the first direction and is provided in the end part.

公开(公告)号：US20180254285A1

公开(公告)日：2018-09-06

申请号：US15970462

申请日：2018-05-03

Applicant: SK hynix Inc.

Inventor： Ki Hong LEE ,  Ji Yeon BAEK ,  Seung Ho PYI

IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/76898 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

公开(公告)号：US20180254284A1

公开(公告)日：2018-09-06

申请号：US15805760

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Min Hwang ,  Jang-Gn Yun ,  Joon-Sung Lim

IPC: H01L27/11575 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00 ,  G11C16/26 ,  G11C16/10

CPC classification number: H01L27/11575 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L23/562 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a memory cell region and an insulator on a portion of the memory cell region. The semiconductor memory device includes a stress relief material that is in the insulator and is between the memory cell region and another region of the semiconductor memory device.

公开(公告)号：US20180254279A1

公开(公告)日：2018-09-06

申请号：US15967930

申请日：2018-05-01

Applicant: Toshiba Memory Corporation

Inventor： Naoki Yasuda

IPC: H01L27/1157 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02326 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US20180254247A1

公开(公告)日：2018-09-06

申请号：US15822329

申请日：2017-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-woo KIM ,  Joon-sung LIM ,  Jang-gn YUN ,  Sung-min Hwang

IPC: H01L23/532 ,  H01L27/11531 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L23/53295 ,  H01L23/5226 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/1207

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

公开(公告)号：US20180247952A1

公开(公告)日：2018-08-30

申请号：US15961334

申请日：2018-04-24

Applicant: Renesas Electronics Corporation

Inventor： Shibun TSUDA

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78 ,  H01L27/11573 ,  H01L27/088

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/762 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7856 ,  H01L29/792

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, a plurality of first projecting portions which include portions of the semiconductor substrate provided in a first region of the semiconductor substrate to extend in a first direction along the main surface of the semiconductor substrate and to be spaced apart from each other in a second direction, orthogonal to the first direction, along the main surface of the semiconductor substrate, a first isolation region provided between the first projecting portions adjacent to each other, and first and second transistors provided in and over an upper part of each of the first projecting portions which is exposed from an upper surface of the first isolation region to be adjacent to each other in the first direction.