公开(公告)号：US20240290651A1

公开(公告)日：2024-08-29

申请号：US18655567

申请日：2024-05-06

申请人： Intel Corporation

发明人： Florian Gstrein ,  Eungnak Han ,  Manish Chandhok ,  Gurpreet Singh

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/7681 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2221/1036

摘要： Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

公开(公告)号：US12074138B2

公开(公告)日：2024-08-27

申请号：US18378978

申请日：2023-10-11

申请人： Intel Corporation

发明人： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC分类号： H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

摘要： Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US12074061B2

公开(公告)日：2024-08-27

申请号：US17407083

申请日：2021-08-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Sheng-Tsung Wang ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Sung-Li Wang ,  Chih-Hao Wang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/76846 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

摘要： A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

公开(公告)号：US12073170B2

公开(公告)日：2024-08-27

申请号：US18354423

申请日：2023-07-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jung-Chan Yang ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu ,  Stefan Rusu

IPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H03K19/094 ,  H01L23/522

CPC分类号： G06F30/394 ,  H01L21/76 ,  H01L23/528 ,  H01L23/5286 ,  H03K19/094 ,  H01L23/5226 ,  H01L2924/0002

摘要： An integrated circuit structure includes a first, second and third power rail extending in a first direction, a first, second and third set of conductive structures extending in the second direction, and being located at a second level, and a first, second and third conductive structure extending in the second direction, and being located at a third level. The first conductive structure overlaps a first conductive structure of the corresponding first, second and third set of conductive structures. The second conductive structure overlaps a second conductive structure of the corresponding first, second and third set of conductive structures. The third conductive structure overlaps a third conductive structure of the corresponding first, second and third set of conductive structures.

公开(公告)号：US20240282728A1

公开(公告)日：2024-08-22

申请号：US18652868

申请日：2024-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/31 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/02 ,  H01L24/03 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2924/1033

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US20240282698A1

公开(公告)日：2024-08-22

申请号：US18650166

申请日：2024-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Wei Chang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Fang-Wei Lee

IPC分类号： H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266

摘要： In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

公开(公告)号：US20240282697A1

公开(公告)日：2024-08-22

申请号：US18645455

申请日：2024-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76846 ,  H01L23/5283

摘要： In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a substrate. A liner layer is arranged along a sidewall of the substrate within a cross-sectional view. A conductive 2D material is arranged on the liner layer within the cross-sectional view. The conductive 2D material includes a top surface that is above a top surface of the liner layer. A conductive structure continuously extends from above a top of the conductive 2D material to below a bottom of the conductive 2D material. The conductive 2D material and the liner layer laterally separate the substrate from the conductive structure.

公开(公告)号：US20240282695A1

公开(公告)日：2024-08-22

申请号：US18231092

申请日：2023-08-07

申请人： SK hynix Inc.

发明人： Jae Ho KIM

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L29/10

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L29/1037 ,  H10B41/27 ,  H10B43/27 ,  H10B63/84

摘要： The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack including a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked, a channel plug formed on a cell region by vertically passing through the stack, a plurality of support structures formed on a contact region by vertically passing through the stack, and a sacrificial layer surrounding a lower end portion sidewall of each of the plurality of support structures.

公开(公告)号：US20240282630A1

公开(公告)日：2024-08-22

申请号：US18169984

申请日：2023-02-16

申请人： International Business Machines Corporation

发明人： Oscar van der Straten ,  Shanti Pancharatnam ,  Chih-Chao Yang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76879 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266

摘要： A semiconductor structure that includes: a plurality of metal wires, and at least one dielectric substrate surrounding the plurality of metal wires. Each of the plurality of metal wires includes a tapered upper portion, a tapered lower portion, and a middle portion between the tapered upper portion and the tapered lower portion that is wider than the tapered upper and lower portions.

公开(公告)号：US20240282624A1

公开(公告)日：2024-08-22

申请号：US18649389

申请日：2024-04-29

申请人： Intel Corporation

发明人： Sean KING ,  Hui Jae YOO ,  Sreenivas KOSARAJU ,  Timothy GLASSMAN

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76831 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002

摘要： Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.