- 专利标题: SELF-ASSEMBLED GUIDED HOLE AND VIA PATTERNING OVER GRATING
-
申请号: US18655567申请日: 2024-05-06
-
公开(公告)号: US20240290651A1公开(公告)日: 2024-08-29
- 发明人: Florian Gstrein , Eungnak Han , Manish Chandhok , Gurpreet Singh
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522
摘要:
Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.
信息查询
IPC分类: