公开(公告)号：US20230005852A1

公开(公告)日：2023-01-05

申请号：US17940081

申请日：2022-09-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/31 ,  H01L23/50

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US09184282B2

公开(公告)日：2015-11-10

申请号：US13963658

申请日：2013-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tzu-Ming Huang ,  Chia-Chia Kan ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66613 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： Embodiments for the present disclosure include a semiconductor device, an ultra-high voltage (UHV) laterally-diffused metal-oxide-semiconductor (LDMOS) transistor, and methods of forming the same. An embodiment includes a first well region of a first conductivity type in a top surface of a substrate, and a second well region of a second conductivity type in the top surface of the substrate. The second well region laterally separated from the first well region by a portion of the substrate. The embodiment further includes a third region of the second conductivity type in the first well region, and a first field oxide region in the first well region, a second field oxide region in the second well region, the second field oxide region having a second bottom surface, and the first field oxide region having a first bottom surface lower than the second bottom surface and on and directly contacting the third region.

摘要翻译： 本公开的实施例包括半导体器件，超高电压（UHV）横向扩散金属氧化物半导体（LDMOS）晶体管及其形成方法。 一个实施例包括在衬底的顶表面中的第一导电类型的第一阱区域和在衬底的顶表面中的第二导电类型的第二阱区域。 第二阱区域由衬底的一部分与第一阱区域横向分离。 该实施例还包括第一阱区中的第二导电类型的第三区域和第一阱区域中的第一场氧化物区域，第二阱区域中的第二场氧化物区域，第二场氧化物区域具有第二底部区域 表面，并且第一场氧化物区域具有比第二底表面低的第一底表面，并且直接接触第三区域。

公开(公告)号：US11444046B2

公开(公告)日：2022-09-13

申请号：US17004467

申请日：2020-08-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/50 ,  H01L23/29

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US12002774B2

公开(公告)日：2024-06-04

申请号：US17940081

申请日：2022-09-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/29

CPC分类号： H01L24/05 ,  H01L23/31 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/02 ,  H01L24/03 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2924/1033

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.

公开(公告)号：US10461183B2

公开(公告)日：2019-10-29

申请号：US15882193

申请日：2018-01-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsai-Feng Yang ,  Chih-Heng Shen ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/423

摘要： A device having a drain region with a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The semiconductor device also comprises a source region spaced from and surrounding the drain region in the first layer.

公开(公告)号：US09882046B2

公开(公告)日：2018-01-30

申请号：US15094605

申请日：2016-04-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsai-Feng Yang ,  Chih-Heng Shen ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang

IPC分类号： H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/423

CPC分类号： H01L29/7823 ,  H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7824

摘要： A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion are formed having a same doping type and a different doping concentration than the drain rectangular portion.

公开(公告)号：US09748377B2

公开(公告)日：2017-08-29

申请号：US14886314

申请日：2015-10-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Ming Huang ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Chih-Heng Shen ,  Po-Tao Chu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A semiconductor device includes a gate structure, a source region and a drain region. The source region and the drain region are on opposite sides of the gate structure. The source region includes a first region of a first conductivity type and a second region of a second conductivity type. The second conductivity type is opposite to the first conductivity type. The first region is between the second region and the gate structure. The second region includes at least one projection protruding into the first region and toward the gate structure.

公开(公告)号：US20160225899A1

公开(公告)日：2016-08-04

申请号：US15094605

申请日：2016-04-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsai-Feng Yang ,  Chih-Heng Shen ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L29/7823 ,  H01L27/0266 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66696 ,  H01L29/7816 ,  H01L29/7824

摘要： A method includes forming a drain region in a first layer on a semiconductor substrate. The drain region is formed comprising a drain rectangular portion having a first end and a second end, a first drain end portion contiguous with the drain rectangular portion and extending from the first end of the drain rectangular portion away from a center of the drain region, and a second drain end portion contiguous with the drain rectangular portion and extending from the second end of the drain rectangular portion away from the center of the drain region. The method also comprises forming a source region free from contact with and surrounding the drain region in the first layer. The first drain end portion and the second drain end portion are formed having a same doping type and a different doping concentration than the drain rectangular portion.

摘要翻译： 一种方法包括在半导体衬底上的第一层中形成漏区。 漏极区域形成为包括具有第一端和第二端的漏极矩形部分，与漏极矩形部分相邻并从漏极矩形部分的第一端延伸离开漏极区域的中心的第一漏极端部分， 以及与排水矩形部分相邻并从排水矩形部分的第二端延伸远离排出区域的中心的第二排水端部分。 该方法还包括形成与第一层中的漏极区不接触并围绕其的区域的源区。 第一漏极端部和第二漏极端部形成为具有与漏极矩形部分相同的掺杂类型和不同的掺杂浓度。

公开(公告)号：US09166046B2

公开(公告)日：2015-10-20

申请号：US14181430

申请日：2014-02-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tzu-Ming Huang ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Chih-Heng Shen ,  Po-Tao Chu

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： A semiconductor device includes a gate structure, and a source region and a drain region on opposite sides of the gate structure. The source region comprises a first region of a first conductivity type, and a second region of a second conductivity type, the second conductivity type opposite to the first conductivity type. The first region is arranged between the second region and the gate structure. The second region comprises at least one projection protruding into the first region and toward the gate structure.

摘要翻译： 半导体器件包括栅极结构，以及栅极结构的相对侧上的源极区域和漏极区域。 源区包括第一导电类型的第一区域和第二导电类型的第二区域，第二导电类型与第一导电类型相反。 第一区域布置在第二区域和栅极结构之间。 第二区域包括突出到第一区域中并朝向栅极结构的至少一个突起。

公开(公告)号：US20240282728A1

公开(公告)日：2024-08-22

申请号：US18652868

申请日：2024-05-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Hong Chang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/50 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/31 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/02 ,  H01L24/03 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/564 ,  H01L2224/03831 ,  H01L2224/0391 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2924/1033

摘要： An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.