公开(公告)号：US20160379713A1

公开(公告)日：2016-12-29

申请号：US15152391

申请日：2016-05-11

Applicant: Renesas Electronics Corporation

Inventor： Tsuyoshi ARIGANE ,  Daisuke Okada ,  Digh Hisamoto

IPC: G11C16/04 ,  H01L29/51 ,  H01L27/115 ,  G11C16/14 ,  H01L29/423

CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

公开(公告)号：US20160343430A1

公开(公告)日：2016-11-24

申请号：US15112748

申请日：2014-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Warren Jackson ,  Gary Gibson

IPC: G11C13/00 ,  G11C16/04 ,  H01L45/00

CPC classification number: G11C13/0002 ,  G11C16/0466 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.

Abstract translation: 公开了一种电荷捕获忆阻器。 示例性电荷俘获忆阻器包括配置在通道的相对侧上的第一电极和第二电极，以在通道上产生电位和电荷屏障。 示例性电荷俘获忆阻器还包括构造成在其中存储和释放电荷的电荷捕获材料，其中存储和释放电荷改变通道的电特性。

公开(公告)号：US20160314848A1

公开(公告)日：2016-10-27

申请号：US15201108

申请日：2016-07-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Naoya TOKIWA

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3445

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

公开(公告)号：US20160307637A1

公开(公告)日：2016-10-20

申请号：US15076519

申请日：2016-03-21

Applicant: NEO Semiconductor, Inc.

Inventor： Fu-Chang Hsu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C16/3427

Abstract: A SONOS byte-erasable EEPROM is disclosed. In one aspect, an apparatus includes a plurality of SONOS memory cells forming an EEPROM memory array. The apparatus also includes a controller that generates bias voltages to program and erase the memory cells. The controller performs a refresh operation when programming selected memory cells to reduce write-disturb on unselected memory cells to prevent data loss.

Abstract translation: 公开了一种SONOS字节可擦除EEPROM。 一方面，一种装置包括形成EEPROM存储器阵列的多个SONOS存储单元。 该装置还包括产生偏置电压以对存储器单元进行编程和擦除的控制器。 编程所选择的存储单元时，控制器执行刷新操作，以减少未选择的存储单元的写入干扰，以防止数据丢失。

公开(公告)号：US09449699B2

公开(公告)日：2016-09-20

申请号：US15009856

申请日：2016-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Won-Taeck Jung ,  Junghoon Park

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3418 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

Abstract: An erase method of a nonvolatile memory includes supplying an erase voltage to a substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within a memory block of the nonvolatile memory, supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, and thereafter floating the word lines connected with the unselected sub-block.

公开(公告)号：US20160268445A1

公开(公告)日：2016-09-15

申请号：US15011510

申请日：2016-01-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi AMO

IPC: H01L29/792 ,  H01L29/94 ,  H01L29/66

CPC classification number: H01L29/945 ,  G11C16/0466 ,  H01L27/0629 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66181 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Abstract translation: 在包括分离栅型MONOS存储器的半导体器件和沟槽电容器元件中，其上部电极部分地嵌入形成在半导体衬底的主表面中的沟槽中，并入其中，上电极的顶表面的平坦度嵌入 沟渠得到改善。 形成在半导体衬底上以形成形成MONOS存储器的存储单元的控制栅电极的多晶硅膜被嵌入形成在电容器元件形成区域中的半导体衬底的主表面中的沟槽中，从而形成上电极，包括 沟槽中的多晶硅膜。

公开(公告)号：US20160268436A1

公开(公告)日：2016-09-15

申请号：US15065156

申请日：2016-03-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinobu ASAMI

IPC: H01L29/786 ,  G11C16/26 ,  H01L27/115 ,  G11C16/10 ,  H01L29/04 ,  H01L29/788

CPC classification number: H01L29/7869 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  H01L27/0705 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/1233 ,  H01L27/1237 ,  H01L27/127 ,  H01L29/045 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/788 ,  H01L2029/42388

Abstract: A highly integrated semiconductor device that holds data and includes a first semiconductor layer, a first gate insulating film over the first semiconductor layer, a first gate electrode over the first gate insulating film, a second semiconductor layer over the first gate electrode, a conductive layer over the second semiconductor layer, a second gate insulating film covering the second semiconductor layer and the conductive layer, and a second gate electrode covering at least part of a side surface of the second semiconductor layer with the second gate insulating film interposed therebetween. An end portion of the second semiconductor layer is substantially aligned with an end portion of the conductive layer.

Abstract translation: 一种高度集成的半导体器件，其保存数据并包括第一半导体层，第一半导体层上的第一栅极绝缘膜，第一栅极绝缘膜上的第一栅电极，第一栅极上的第二半导体层，导电层 覆盖所述第二半导体层的第二栅极绝缘膜，覆盖所述第二半导体层和所述导电层的第二栅极绝缘膜，以及覆盖所述第二半导体层的侧表面的至少一部分的第二栅电极，其间插入有所述第二栅极绝缘膜。 第二半导体层的端部基本上与导电层的端部对准。

公开(公告)号：US20160260490A1

公开(公告)日：2016-09-08

申请号：US15063060

申请日：2016-03-07

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Jong Ho LEE ,  Ho Jung KANG ,  Nag Yong CHOI ,  Byeong Il HAN ,  Kyoung Jin PARK ,  Sung Yong CHUNG

IPC: G11C16/16 ,  H01L27/115

CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3472 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792

Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.

Abstract translation: 数据存储装置包括非易失性存储装置，其包括包括多个存储单元的存储单元阵列和控制电路。 每个存储单元包括沟道层，沟道层上的电荷陷阱层和电荷陷阱层上的控制电极，电荷陷阱层由存储单元共享。 电荷陷阱层包括分别设置在存储单元的控制电极下方的编程区域和电荷扩展阻挡区域，每个区域设置在两个相邻的编程区域之间和两个相邻的控制电极之间。 控制电路控制存储单元阵列，从而通过以与存储在程序区域中的程序电荷具有相同极性的电荷充电电荷扩展阻挡区域，在电荷扩展阻挡区域中产生势垒。

公开(公告)号：US09437736B2

公开(公告)日：2016-09-06

申请号：US14215536

申请日：2014-03-17

Applicant: Floadia Corporation

Inventor： Yasuhiro Taniguchi ,  Kosuke Okuyama

IPC: H01L29/788 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/792 ,  G11C16/04

CPC classification number: H01L29/7841 ,  G11C16/0466 ,  H01L29/4234 ,  H01L29/66659 ,  H01L29/788 ,  H01L29/792

Abstract: In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device.

Abstract translation: 在非易失性半导体存储器件中，只需要在数据写入时在高电阻区域中产生电压降。 因此，与传统的器件相比，可以减小施加到栅电极的电压值。 与施加电压值的降低相对应，可以降低存储晶体管的栅极绝缘膜的膜厚度，还可以降低用于控制存储晶体管的外围晶体管的栅极绝缘膜的膜厚。 结果，与常规器件相比，非易失性半导体存储器件的电路结构可以减小。

公开(公告)号：US09412462B2

公开(公告)日：2016-08-09

申请号：US14798561

申请日：2015-07-14

Applicant: Seoul National University R&DB FOUNDATION

Inventor： Byung-Gook Park ,  Sang-Ho Lee

IPC: G11C16/04 ,  G11C16/34 ,  H01L27/115

CPC classification number: G11C16/34 ,  G11C8/12 ,  G11C8/14 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/0483 ,  G11C2213/71 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

Abstract: This invention provides 3D stacked memory arrays and methods for determining threshold voltages of string selection transistors by LSMP (layer selection by multi-level permutation) for enabling to select layers regardless of the number or as many as possible by the limited numbers of threshold voltage states and SSLs. Thus, this invention enables to maximize the degree of integrity of memory by minimizing the number of SSLs and to select layers with no limitation of the number by considering a recent aspect ratio of the semiconductor etching process.

Abstract translation: 本发明提供了3D堆叠存储器阵列和用于通过LSMP（通过多电平置换的层选择）来确定串选择晶体管的阈值电压的方法，用于使得能够选择层，而不管数量多少或尽可能多的限制数量的阈值电压状态 和SSL。 因此，本发明能够通过最小化SSL的数目来最大限度地提高存储器的完整性程度，并且通过考虑半导体蚀刻工艺的最近的纵横比来选择不受数量限制的层。