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公开(公告)号：US10026477B2
公开(公告)日：2018-07-17
申请号：US15329845
申请日：2015-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Ning Ge , John Paul Strachan , Gary Gibson , Warren Jackson
Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
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公开(公告)号：US20160351622A1
公开(公告)日：2016-12-01
申请号：US15114010
申请日：2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gary Gibson , Warren Jackson , R. Stanley Williams
CPC classification number: H01L27/2418 , G11C7/04 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/73 , G11C2213/76 , H01L45/00 , H01L45/1286 , H01L45/145
Abstract: A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.
Abstract translation: 具有负差分电阻的区域的电路部件包括：第一层材料; 以及与所述第一材料层接触的第二材料层，所述接触件形成第一自加热界面。 第一自加热界面被构造成使得从第一材料层流向第二层材料的电流遇到在第一界面处发生的电阻抗大于在第一和第二层中发生的任何电阻抗 材料，其中在第一界面处发生的加热由由在第一界面处发生的电阻抗引起的焦耳加热主导，并且其中在第一界面处发生的电阻抗随温度升高而降低，以引起负差分电阻的区域。
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公开(公告)号：US20160351802A1
公开(公告)日：2016-12-01
申请号：US15111515
申请日：2014-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Warren Jackson , Gary Gibson , R. Stanley Williams , Jianhua Yang
CPC classification number: H01L45/12 , G11C13/003 , H01L27/2418 , H01L45/00
Abstract: A nonlinear dielectric stack circuit element includes a first layer of material having a first dielectric constant; a second layer of material having a second dielectric constant; and a third layer of material sandwiched between the first layer of material and the second layer of material and having a third dielectric constant. The third dielectric constant has a value less than the first dielectric constant and the second dielectric constant.
Abstract translation: 非线性介质堆叠电路元件包括具有第一介电常数的第一材料层; 具有第二介电常数的第二材料层; 以及夹在所述第一材料层和所述第二材料层之间并具有第三介电常数的第三材料层。 第三介电常数的值小于第一介电常数和第二介电常数。
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公开(公告)号：US20160343938A1
公开(公告)日：2016-11-24
申请号：US15114973
申请日：2014-03-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gary Gibson , Richard Henze , Warren Jackson , Yoocharn Jeon
CPC classification number: H01L45/1293 , G11C13/004 , G11C13/0069 , G11C2013/0095 , H01L27/2418 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
Abstract: A memristor device with a thermally-insulating cladding includes a first electrode, a second electrode, a memristor, and a thermally-insulating cladding. The memristor is coupled in electrical series between the first electrode and the second electrode. The thermally-insulating cladding surrounds at least a portion of the memristor.
Abstract translation: 具有绝热包层的回忆体装置包括第一电极，第二电极，忆阻器和绝热包层。 忆阻器以第一电极和第二电极之间的电气系列耦合。 绝热包层围绕至少一部分忆阻器。
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公开(公告)号：US20160254448A1
公开(公告)日：2016-09-01
申请号：US15032913
申请日：2013-11-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Byungjoon Choi , Jianhua Yang , R. Stanley Williams , Gary Gibson , Warren Jackson
IPC: H01L45/00
CPC classification number: H01L45/1226 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN: XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
Abstract translation: 具有三层选择器的非线性忆阻器装置包括与三层选择器电连接的忆阻器。 忆阻器包括至少一个导电层和至少一个电绝缘层。 三层选择器包括从XN-XO-XN组成的组中选择的三层结构; XN-YO-ZN：XN-YO-XN; XO-XN-XO; XO-YN-XO; XO-YN-ZO; XO-YO-XO; XO-YO-ZO; XN-YN-ZN; 和XN-YN-XN，X表示不同于Y和Z的化合物形成金属。
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公开(公告)号：US09905757B2
公开(公告)日：2018-02-27
申请号：US15032913
申请日：2013-11-12
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Byungjoon Choi , Jianhua Yang , R. Stanley Williams , Gary Gibson , Warren Jackson
CPC classification number: H01L45/1226 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN; XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
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公开(公告)号：US09812500B2
公开(公告)日：2017-11-07
申请号：US15114010
申请日：2014-01-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Gary Gibson , Warren Jackson , R. Stanley Williams
CPC classification number: H01L27/2418 , G11C7/04 , G11C11/1659 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C2213/73 , G11C2213/76 , H01L45/00 , H01L45/1286 , H01L45/145
Abstract: A circuit component that exhibits a region of negative differential resistance includes: a first layer of material; and a second layer of material in contact with the first layer of material, the contact forming a first self-heating interface. The first self-heating interface is structured such that an electrical current flowing from the first layer of material to the second layer of material encounters an electrical impedance occurring at the first interface that is greater than any electrical impedance occurring in the first and second layers of material, wherein heating occurring at the first interface is dominated by Joule heating caused by the electrical impedance occurring at the first interface, and wherein the electrical impedance occurring at the first interface decreases with increasing temperature to induce a region of negative differential resistance.
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公开(公告)号：US20170271591A1
公开(公告)日：2017-09-21
申请号：US15500050
申请日：2015-02-13
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Jianhua Yang , Kyung Min Kim , Zhiyong Li
CPC classification number: H01L45/147 , G11C13/0007 , G11C13/0069 , G11C2013/0083 , G11C2213/73 , G11C2213/77 , H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/16
Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.
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公开(公告)号：US09747976B2
公开(公告)日：2017-08-29
申请号：US15112748
申请日：2014-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Gary Gibson
CPC classification number: G11C13/0002 , G11C16/0466 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.
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公开(公告)号：US20160343430A1
公开(公告)日：2016-11-24
申请号：US15112748
申请日：2014-01-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Warren Jackson , Gary Gibson
CPC classification number: G11C13/0002 , G11C16/0466 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
Abstract: A charge trapping memristor is disclosed. An example charge trapping memristor includes a first electrode and second electrode configured on opposite sides of a channel to generate an electric potential across the channel, and a charge barrier. The example charge trapping memristor also includes a charge trapping material configured to store and release an electric charge therein, wherein storing and releasing the electric charge changes electrical properties of the channel.
Abstract translation: 公开了一种电荷捕获忆阻器。 示例性电荷俘获忆阻器包括配置在通道的相对侧上的第一电极和第二电极，以在通道上产生电位和电荷屏障。 示例性电荷俘获忆阻器还包括构造成在其中存储和释放电荷的电荷捕获材料，其中存储和释放电荷改变通道的电特性。
