公开(公告)号：US20190012105A1

公开(公告)日：2019-01-10

申请号：US16029454

申请日：2018-07-06

Applicant: SAP SE

Inventor： Ivan Schreter

IPC: G06F3/06 ,  G06F12/0802 ,  G06F17/30

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0673 ,  G06F11/1446 ,  G06F11/1471 ,  G06F11/1658 ,  G06F12/0802 ,  G06F12/1009 ,  G06F16/128 ,  G06F16/134 ,  G06F16/162 ,  G06F16/176 ,  G06F16/1824 ,  G06F16/215 ,  G06F16/2358 ,  G06F16/245 ,  G06F16/24552 ,  G06F16/27 ,  G06F16/951 ,  G06F17/30088 ,  G06F2201/84 ,  G06F2201/85 ,  G06F2212/604 ,  G06F2212/652 ,  H04L67/1097 ,  H04L67/2809 ,  H04L67/2842 ,  H04L69/40

Abstract: A method can include caching, at a first computing node and a second computing node, a replica of an anchor object. The anchor object can link to a topology object storing elements comprising a distributed data storage system. The first computing node can reside in a first availability zone. The second computing node can reside in a second availability zone. The first availability zone and the second availability zone can be part of a data center. The first computing node and the second computing node can each store a data partition associated with a data container belonging to a tenant. A replica of the topology object can be cached at the first availability zone and the second availability zone. A query requiring data associated with the tenant can be executed based on the cached replica of the anchor objects and/or topology objects.

公开(公告)号：US20180239714A1

公开(公告)日：2018-08-23

申请号：US15437581

申请日：2017-02-21

Applicant: ARM Limited

Inventor： ABHISHEK RAJA ,  Michael FILIPPO

IPC: G06F12/1045 ,  G06F12/0864 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/502 ,  G06F2212/6032 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/681

Abstract: An apparatus and method are provided for making efficient use of address translation cache resources. The apparatus has an address translation cache having a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Each item of address translation data has a page size indication for a page within the memory system that is associated with that address translation data. Allocation circuitry performs an allocation process to determine the address translation data to be stored in each entry. Further, mode control circuitry is used to switch a mode of operation of the apparatus between a non-skewed mode and at least one skewed mode, dependent on a page size analysis operation. The address translation cache is organised as a plurality of portions, and in the non-skewed mode the allocation circuitry is arranged, when performing the allocation process, to permit the address translation data to be allocated to any of the plurality of portions. In contrast, when in the at least one skewed mode, the allocation circuitry is arranged to reserve at least one portion for allocation of address translation data associated with pages of a first page size and at least one other portion for allocation of address translation data associated with pages of a second page size different to the first page size.

公开(公告)号：US20180196750A1

公开(公告)日：2018-07-12

申请号：US15401041

申请日：2017-01-08

Applicant: Apple Inc.

Inventor： Ben Shilo ,  Arie Peled ,  Tal Ostro

IPC: G06F12/0808 ,  H04L29/08 ,  G06F3/06 ,  G06F12/128

CPC classification number: G06F12/0808 ,  G06F3/0607 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0868 ,  G06F2212/1024 ,  G06F2212/222 ,  G06F2212/652 ,  H04L67/2833 ,  H04L67/2842

Abstract: A storage device includes a nonvolatile memory and a controller. The controller is configured to store in the nonvolatile memory data for a host, to generate messages having a message size to be cached in the host in a cache memory having a cache-line size larger than the message size, to aggregate two or more of the messages by producing an aggregated message that matches the cache-line size, and to send the aggregated message to the host.

公开(公告)号：US20180081816A1

公开(公告)日：2018-03-22

申请号：US15273433

申请日：2016-09-22

Applicant: Google Inc.

Inventor： Joel Dylan Coburn ,  Albert Borchers ,  Christopher Lyle Johnson ,  Robert S. Sprinkle

IPC: G06F12/0868 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/12 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/0868 ,  G06F12/023 ,  G06F12/04 ,  G06F12/0815 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/3042 ,  G06F2212/305 ,  G06F2212/604 ,  G06F2212/652

Abstract: Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

公开(公告)号：US09880770B2

公开(公告)日：2018-01-30

申请号：US15013855

申请日：2016-02-02

Applicant: SK Hynix Inc.

Inventor： Fan Zhang ,  Taeil Um ,  Yu Cai

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/652 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: Techniques and systems are provided for tracking commands. Such methods and systems can include maintaining a meta page in a volatile memory to track commands. The meta page can comprise information associated with a non-volatile memory superblock. When an invalidation command is received for a first logical address, the first logical address can be stored along with an indication that the data associated with the first logical address is invalid, in a first location in the meta page.

公开(公告)号：US09767038B2

公开(公告)日：2017-09-19

申请号：US15276664

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/12 ,  G06F12/1027 ,  G06F12/0802 ,  G06F12/1045 ,  G06F12/0875

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0875 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/608 ,  G06F2212/651 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/681 ,  G06F2212/684

Abstract: Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address.

公开(公告)号：US09740628B2

公开(公告)日：2017-08-22

申请号：US13785212

申请日：2013-03-05

Applicant: International Business Machines Corporation

Inventor： Anthony J. Bybell ,  Michael K. Gschwind

IPC: G06F12/00 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/652 ,  G06F2212/683

Abstract: A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry, determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous, and setting a marker in the page table for indicating that the main storage pages of identified by the first PTE and second PTEs are contiguous.

公开(公告)号：US09519430B2

公开(公告)日：2016-12-13

申请号：US14288979

申请日：2014-05-28

Applicant: International Business Machines Corporation

Inventor： Alfred F. Foster ,  Robert Miller, Jr. ,  Thomas F. Rankin

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F11/22

CPC classification number: G06F3/0614 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0671 ,  G06F3/0683 ,  G06F3/0689 ,  G06F9/00 ,  G06F11/22 ,  G06F12/0284 ,  G06F12/0623 ,  G06F12/08 ,  G06F12/0842 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/261 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.

Abstract translation: 描述了一种在多个地址空间中通过多线程触发器验证对真实存储的管理的方法，系统和计算机程序产品。 该方法包括基于可用处理器的数量来动态地缩放多个工作单元和多个地址空间，并且动态地缩放表示由每个工作单元数量访问的虚拟存储器的存储页面的数量和页面大小基于 总可用内存 该方法还包括在每个工作单元中获得不同类型的存储帧大小和属性，访问与各种不同类型的存储帧大小和属性相对应的存储页面并执行相应的功能，并且对于每个 执行相应功能的工作单元，存储页面的位置和存储页面的内容基于相应的功能。

公开(公告)号：US09483412B2

公开(公告)日：2016-11-01

申请号：US14516192

申请日：2014-10-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Wade K. Smith

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/0826 ,  G06F2212/622 ,  G06F2212/652

Abstract: A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. A second page table entry is generated from the first page table entry to be stored with the first page table entry. The second page table entry provides address information for the second page. The second page table entry has a configuration that is compatible with the first cache.

Abstract translation: 用于将页表条目存储在第一高速缓存中的装置和方法。 接收到具有片段字段的第一页表条目，该片段字段包含所请求的第一页的地址信息和与第一页逻辑上相邻的至少第二页。 从第一页表条目生成第二页表条目以与第一页表条目一起存储。 第二页表项提供第二页的地址信息。 第二页表条目具有与第一高速缓存兼容的配置。

公开(公告)号：US09465736B2

公开(公告)日：2016-10-11

申请号：US15090890

申请日：2016-04-05

Applicant: International Business Machines Corporation

Inventor： Alfred F. Foster ,  Robert Miller, Jr. ,  Thomas F. Rankin

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/06

CPC classification number: G06F3/0614 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0671 ,  G06F3/0683 ,  G06F3/0689 ,  G06F9/00 ,  G06F11/22 ,  G06F12/0284 ,  G06F12/0623 ,  G06F12/08 ,  G06F12/0842 ,  G06F2212/1008 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/261 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/656 ,  G06F2212/657

Abstract: A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.