公开(公告)号：US20210064533A1

公开(公告)日：2021-03-04

申请号：US16552001

申请日：2019-08-27

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Michael FILIPPO

IPC: G06F12/0875

Abstract: A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.

公开(公告)号：US20210064377A1

公开(公告)日：2021-03-04

申请号：US16550612

申请日：2019-08-26

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Rakesh Shaji LAL ,  Michael FILIPPO ,  Glen Andrew HARRIS ,  Vasu KUDARAVALLI ,  Huzefa Moiz SANJELIWALA ,  Jason SETTER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/34

Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.

公开(公告)号：US20190310948A1

公开(公告)日：2019-10-10

申请号：US15945900

申请日：2018-04-05

Applicant: Arm Limited

Inventor： ABHISHEK RAJA ,  Michael FILIPPO

IPC: G06F12/1027

Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data. Lookup circuitry is responsive to an access request associated with a target virtual address, to perform a lookup process employing a target hash value computed from the plurality of source values used to generate the target virtual address, in order to identify any candidate matching entry in the address translation cache. When there is at least one candidate matching entry, a virtual address check process is then performed in order to determine whether any candidate matching entry is an actual matching entry whose address translation data enables the target virtual address to be translated to a corresponding target physical address. Such an approach can significantly improve the performance of accesses to the address translation cache, and can also give rise to power consumption savings.

公开(公告)号：US20180121203A1

公开(公告)日：2018-05-03

申请号：US15335741

申请日：2016-10-27

Applicant: ARM LIMITED

Inventor： Yasuo ISHII ,  Michael FILIPPO ,  Muhammad Umar FAROOQ

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806

Abstract: An apparatus comprises a branch target buffer (BTB) to store predicted target addresses of branch instructions. In response to a fetch block address identifying a fetch block comprising two or more program instructions, the BTB performs a lookup to identify whether it stores one or more predicted target addresses for one or more branch instructions in the fetch block. When the BTB is identified in the lookup as storing predicted target addresses for more than one branch instruction in said fetch block, branch target selecting circuitry selects a next fetch block address from among the multiple predicted target addresses returned in the lookup. A shortcut path bypassing the branch target selecting circuitry is provided to forward a predicted target address identified in the lookup as the next fetch block address when a predetermined condition is satisfied.

公开(公告)号：US20210026627A1

公开(公告)日：2021-01-28

申请号：US16521748

申请日：2019-07-25

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Michael FILIPPO ,  Huzefa Moiz SANJELIWALA ,  Kelvin Domnic GOVEAS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction.

公开(公告)号：US20200174947A1

公开(公告)日：2020-06-04

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Dimitrios KASERIDIS ,  Klas Magnus BRUCE ,  Michael FILIPPO ,  Joseph Michael PUSDESRIS ,  Jamshed JALAL

IPC: G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US20180275994A1

公开(公告)日：2018-09-27

申请号：US15464727

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Robert Greg McDONALD ,  Michael FILIPPO ,  Glen Andrew HARRIS

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3001 ,  G06F9/3016

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.

公开(公告)号：US20170371793A1

公开(公告)日：2017-12-28

申请号：US15194902

申请日：2016-06-28

Applicant: ARM Limited

Inventor： Ali SAIDI ,  Kshitij SUDAN ,  Andrew Joseph RUSHING ,  Andreas HANSSON ,  Michael FILIPPO

IPC: G06F12/0871 ,  G06F12/0873 ,  G06F12/0895

CPC classification number: G06F12/0871 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0895 ,  G06F2212/305 ,  G06F2212/401 ,  G06F2212/466

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

公开(公告)号：US20210055962A1

公开(公告)日：2021-02-25

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David ACHENBACH ,  Robert Greg MCDONALD ,  Nicholas Andrew PFISTER ,  Kelvin Domnic GOVEAS ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Zachary Allen KINGSBURY

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/52 ,  G06F9/30

Abstract: An apparatus and method are provided for operating an issue queue. The issue queue has a first section and a second section, where each of those sections comprises a number of entries, and where each entry is employed to store operation information identifying an operation to be performed by a processing unit. Allocation circuitry determines, for each item of received operation information, whether to allocate that operation information to an entry in the first section or to an entry in the second section. The operation information identifies not only the associated operation, but also each source operand required by the associated operation and availability of each source operand. Selection circuitry selects from the issue queue, during a given selection iteration, an operation to be issued to the processing unit, and selects that operation from amongst the operations whose required source operands are available. Availability update circuitry is used to update source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. Further, a deferral mechanism is used to inhibit from selection by the selection circuitry, during at least a next selection iteration following the given selection iteration, any operation associated with an entry in the second section whose required source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration. Such an approach can enable the effective capacity of the issue queue to be increased without adversely impacting the timing of the scheduling functionality performed in respect of the issue queue.

公开(公告)号：US20200167284A1

公开(公告)日：2020-05-28

申请号：US16202171

申请日：2018-11-28

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Mark David WERKHEISER ,  Michael FILIPPO ,  Klas Magnus BRUCE ,  Paul Gilbert MEYER

IPC: G06F12/0815 ,  G06F13/16

Abstract: An apparatus and method are provided for processing ownership upgrade requests in relation to cached data. The apparatus has a plurality of processing units, at least some of which have associated cache storage. A coherent interconnect couples the plurality of master units with memory, the coherent interconnect having a snoop unit used to implement a cache coherency protocol when a request received by the coherent interconnect identifies a cacheable memory address within the memory. Contention management circuitry is provided to control contended access to a memory address by two or more processing units within the plurality of processing units. The coherent interconnect may receive, from a first processing unit having an associated cache storage, an ownership upgrade request specifying a target memory address, the ownership upgrade request indicating that a copy of data at the target memory address, as held in a shared state in the first processing unit's associated cache storage at a time the ownership upgrade request was issued, is required to have its state changed from the shared state to a unique state prior to the first processing circuitry performing a write operation to the data. The coherent interconnect is arranged to process the ownership upgrade request by referencing the snoop unit in order to determine whether the first processing unit's associated cache storage is identified as still holding a copy of the data at the target memory address at a time the ownership upgrade request is processed. In that event, a pass condition is identified for the ownership upgrade request independent of information held by the contention management circuitry for the target memory address.