公开(公告)号：US10164185B2

公开(公告)日：2018-12-25

申请号：US15702136

申请日：2017-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hung Shih ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.

公开(公告)号：US20180138402A1

公开(公告)日：2018-05-17

申请号：US15871559

申请日：2018-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Ting Chu ,  Chia-Shiung Tsai

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/08 ,  H01L45/12 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode disposed over a lower interconnect layer and a data storage layer having a first thickness over the bottom electrode. A capping layer is disposed over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 2 and approximately 3 times thicker than the first thickness. A top electrode is disposed over the capping layer and an upper interconnect layer is disposed over the top electrode.

公开(公告)号：US09966139B2

公开(公告)日：2018-05-08

申请号：US15730398

申请日：2017-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Cheng Chou ,  Yu-Der Chih ,  Wen-Ting Chu

IPC: G11C13/00 ,  H01L27/24 ,  H01L23/522 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79 ,  H01L23/522 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1616

Abstract: A memory architecture includes: a first memory macro comprising a first plurality of memory cells that each comprises a first variable resistance dielectric layer with a first geometry parameter; and a second memory macro comprising a second plurality of memory cells that each comprises a second variable resistance dielectric layer with a second geometry parameter, wherein the first geometry parameter is different from the second geometry parameter thereby causing the first and second memory macros to have first and second endurances. The first and second variable resistance dielectric layers are formed using a single process recipe. The first endurance comprises a maximum number of cycles for which the first plurality of memory cells can transition between first and second logical states, and the second endurance comprises a maximum number of cycles for which the second plurality of memory cells can transition between the first and second logical states.

公开(公告)号：US09947617B2

公开(公告)日：2018-04-17

申请号：US15418904

申请日：2017-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chi Tu ,  Chin-Chieh Yang ,  Wen-Ting Chu

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure relates to an integrated circuit configured to mitigate damage to MIM decoupling capacitors. In some embodiments, the integrated chip has a lower metal interconnect layer arranged over a substrate. A plurality of MIM (metal-insulator-metal) structures are arranged over the lower metal interconnect layer, and a plurality of memory cells are arranged over the lower metal interconnect layer at a location laterally offset from the plurality of MIM structures. An upper metal interconnect layer is arranged over the plurality of MIM structures and the plurality of memory cells. One or both of the lower metal interconnect layer and the upper metal interconnect layer are comprised within a conductive path that electrically couples the plurality of MIM structures in a series connection. The plurality of MIM structures and the plurality of memory cells comprise multi-layer structures having a substantially same shape.

公开(公告)号：US09934853B2

公开(公告)日：2018-04-03

申请号：US15425213

申请日：2017-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Chieh Yang ,  Chih-Yang Chang ,  Chang-Sheng Liao ,  Hsia-Wei Chen ,  Jen-Sheng Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Manish Kumar Singh ,  Chi-Tsai Chen

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/79 ,  G11C2213/82

Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.

公开(公告)号：US20170140820A1

公开(公告)日：2017-05-18

申请号：US15399977

申请日：2017-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hung Shih ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1273 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by forming an initial conductive filament within a dielectric data storage layer of an RRAM cell having a bottom electrode connected to a drain terminal of a PMOS transistor and a top electrode separated from the bottom electrode by the dielectric data storage layer. The initial conductive filament is formed by turning on the PMOS transistor by providing a substantially zero first forming voltage to a gate terminal of the PMOS transistor, by providing a substantially zero second forming voltage to a source terminal of the PMOS transistor, by providing a first non-zero forming voltage to a bulk terminal of the PMOS transistor, and by providing a second non-zero forming voltage to the top electrode.

公开(公告)号：US09647207B2

公开(公告)日：2017-05-09

申请号：US14605023

申请日：2015-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hai-Dang Trinh ,  Chia-Shiung Tsai ,  Chin-Wei Liang ,  Cheng-Yuan Tsai ,  Hsing-Lien Lin ,  Chin-Chieh Yang ,  Wen-Ting Chu

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1675

Abstract: A resistive random access memory (RRAM) cell with a high κ layer based on a group-V oxide and hafnium oxide is provided. The RRAM cell includes a bottom electrode layer, a group-V oxide layer arranged over the bottom electrode layer, and a hafnium oxide based layer arranged over and abutting the group-V oxide layer. The RRAM cell further includes a capping layer arranged over and abutting the hafnium oxide based layer, and a top electrode layer arranged over the capping layer. A method for manufacturing the RRAM cell is also provided.

公开(公告)号：US09601545B1

公开(公告)日：2017-03-21

申请号：US14883808

申请日：2015-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chi Tu ,  Chin-Chieh Yang ,  Wen-Ting Chu

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L23/5223 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure relates to a method of forming an integrated circuit that prevents damage to MIM decoupling capacitors, and an associated structure. In some embodiments, the method comprises forming one or more lower metal interconnect structures within a lower ILD layer over a substrate. A plurality of MIM structures are formed over the lower metal interconnect structures, and one or more upper metal interconnect structures are formed within an upper ILD layer over the plurality of MIM structures. Together the lower and upper metal interconnect structures electrically couple the plurality of MIM structures in a series connection between a first voltage potential and a second voltage potential. By placing the MIM structures in a series connection, dissipation of the first voltage potential (e.g., a supply voltage) is spread out over the MIM structures, thereby reducing the voltage potential difference between electrodes of any one of the MIM structures.

公开(公告)号：US09577009B1

公开(公告)日：2017-02-21

申请号：US14940421

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Hung Shih ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Hsia-Wei Chen ,  Chin-Chieh Yang ,  Jen-Sheng Yang ,  Wen-Ting Chu ,  Yu-Wen Liao

IPC: H01L27/24 ,  H01L45/00 ,  G11C5/14

CPC classification number: H01L45/1273 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0083 ,  G11C2213/79 ,  H01L27/2427 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.

Abstract translation: 本公开涉及包括由PMOS晶体管驱动的RRAM单元的集成芯片以及相关联的形成方法。 在一些实施例中，集成芯片具有布置在半导体衬底内的PMOS晶体管。 电阻RRAM单元布置在覆盖半​​导体衬底的层间电介质（ILD）层内。 RRAM单元具有通过具有可变电阻的介电数据存储层与第二导电电极分离的第一导电电极。 第一导电电极通过一个或多个金属互连层连接到PMOS晶体管的漏极端子。 使用PMOS晶体管来驱动RRAM单元允许减小体效应的影响，因此允许以低功率和短时间执行复位操作。

公开(公告)号：US09553265B1

公开(公告)日：2017-01-24

申请号：US14995294

申请日：2016-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Sheng Yang ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Manish Kumar Singh

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/122 ,  H01L45/146 ,  H01L45/1666 ,  H01L45/1691

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract translation: 本公开涉及集成电路，其包括设置在半导体衬底上的半导体衬底和互连结构。 互连结构包括下金属层，设置在下金属层上的中间金属层和设置在中间金属层上的上金属层。 下金属层的上表面和中间金属层的下表面间隔开第一距离。 电阻随机存取存储器（RRAM）单元布置在下金属层和上金属层之间。 RRAM单元包括由具有可变电阻的数据存储层分离的底部电极和顶部电极。 数据存储层垂直地跨越大于第一距离的第二距离。