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公开(公告)号：US10811394B2
公开(公告)日：2020-10-20
申请号：US16458877
申请日：2019-07-01
Inventor： Chen-Hua Yu , An-Jhih Su , Wei-Yu Chen , Ying-Ju Chen , Tsung-Shu Lin , Chin-Chuan Chang , Hsien-Wei Chen , Wei-Cheng Wu , Li-Hsien Huang , Chi-Hsi Wu , Der-Chyang Yeh
IPC: H01L25/065 , H01L21/56 , H01L21/48 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/00
Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
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公开(公告)号：US10796947B2
公开(公告)日：2020-10-06
申请号：US16217469
申请日：2018-12-12
Inventor： Jack Liu , Wei-Cheng Wu , Charles Chew-Yuen Young , Sing-Kai Huang
IPC: H01L21/00 , H01L21/768 , H01L21/033 , H01L21/02
Abstract: A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
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公开(公告)号：US10672776B2
公开(公告)日：2020-06-02
申请号：US16458970
申请日：2019-07-01
Inventor： Yen-Huei Chen , Hung-Jen Liao , Chih-Yu Lin , Jonathan Tsung-Yung Chang , Wei-Cheng Wu
IPC: G11C11/00 , H01L27/11 , H01L49/02 , G11C11/412 , G11C11/419 , H01L23/522 , H01L23/528 , H01L23/532 , G11C5/02 , G11C5/14
Abstract: A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.
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公开(公告)号：US20200083156A1
公开(公告)日：2020-03-12
申请号：US16685645
申请日：2019-11-15
Inventor： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC: H01L23/498 , H01L23/58 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/31
Abstract: A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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公开(公告)号：US10510674B2
公开(公告)日：2019-12-17
申请号：US16227725
申请日：2018-12-20
Inventor： Yan-Fu Lin , Chen-Hua Yu , Meng-Tsan Lee , Wei-Cheng Wu , Hsien-Wei Chen
IPC: H01L23/538 , H01L23/00 , H01L23/528 , H01L25/10 , H01L23/31 , H01L21/48
Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
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Patent Agency Ranking
公开(公告)号：US20190295955A1
公开(公告)日：2019-09-26
申请号：US16436494
申请日：2019-06-10
Inventor： Cheng-Hsien Hsieh , Li-Han Hsu , Wei-Cheng Wu , Hsien-Wei Chen , Der-Chyang Yeh , Chi-Hsi Wu , Chen-Hua Yu
Abstract: An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern includes a first dummy pattern having a first hole extending through a first conductive region. The device further includes a second metallization pattern over the first metallization pattern. The second metallization pattern includes a second dummy pattern having a second hole extending through a second conductive region. The second hole is arranged projectively overlapping a portion of the first hole and a portion of the first conductive region.
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公开(公告)号：US20190252334A1
公开(公告)日：2019-08-15
申请号：US16390814
申请日：2019-04-22
Inventor： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chen-Hua Yu , Tsung-Shu Lin , Wei-Cheng Wu
CPC classification number: H01L24/05 , H01L21/56 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/481 , H01L23/562 , H01L24/03 , H01L24/11 , H01L24/13 , H01L24/19 , H01L25/105 , H01L25/50 , H01L2224/0231 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/92244 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/35121 , H01L2924/00012 , H01L2924/00
Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.
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公开(公告)号：US10373964B2
公开(公告)日：2019-08-06
申请号：US15864873
申请日：2018-01-08
Inventor： Yen-Huei Chen , Hung-Jen Liao , Chih-Yu Lin , Jonathan Tsung-Yung Chang , Wei-Cheng Wu
IPC: G11C11/00 , H01L27/11 , G11C11/412 , G11C11/419 , H01L23/522 , H01L23/528 , H01L23/532 , H01L49/02 , G11C5/02 , G11C5/14
Abstract: A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell toward a first supply voltage level responsive to a voltage level at a second data node of the memory cell; causing a pass gate of the memory cell to pull the voltage level at the first data node of the memory cell toward a second supply voltage level responsive to a word line signal, the second supply voltage level being different from the first supply voltage level; and limiting a driving capability of the pulling device by a resistive device, the resistive device being electrically coupled between the pulling device and a supply voltage source configured to provide a first supply voltage, the first supply voltage having the first supply voltage level.
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公开(公告)号：US10354961B2
公开(公告)日：2019-07-16
申请号：US15978621
申请日：2018-05-14
Inventor： Chen-Hua Yu , Hsien-Wei Chen , Meng-Tsan Lee , Tsung-Shu Lin , Wei-Cheng Wu , Chien-Chia Chiu , Chin-Te Wang
IPC: H01L23/00 , H01L23/538 , H01L23/31 , H01L21/48 , H01L21/56 , H01L25/10 , H01L25/00 , H01L23/498 , H01L21/683
Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
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公开(公告)号：US20190115300A1
公开(公告)日：2019-04-18
申请号：US16222219
申请日：2018-12-17
Inventor： Chen-Hua Yu , An-Jhih Su , Chi-Hsi Wu , Der-Chyang Yeh , Ming Shih Yeh , Wei-Cheng Wu
IPC: H01L23/538 , H01L21/56 , H01L25/16 , H01L21/768 , H01L21/3105 , H01L23/00 , H01L21/683 , H01L25/065 , H01L25/00
Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.
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