公开(公告)号：US10446400B2

公开(公告)日：2019-10-15

申请号：US15898420

申请日：2018-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic

IPC: H01L21/28 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/49

Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.

公开(公告)号：US10381315B2

公开(公告)日：2019-08-13

申请号：US15927239

申请日：2018-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harsono S. Simka ,  Ganesh Hegde ,  Joon Goo Hong ,  Rwik Sengupta ,  Mark S. Rodder

IPC: H01L31/062 ,  H01L23/00 ,  H01L23/522 ,  H01L27/02 ,  H04L9/32 ,  H01L23/532

Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.

公开(公告)号：US10170549B2

公开(公告)日：2019-01-01

申请号：US14918954

申请日：2015-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/778

Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

公开(公告)号：US09905672B2

公开(公告)日：2018-02-27

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Reddy Palle ,  Joon Goo Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20180053690A1

公开(公告)日：2018-02-22

申请号：US15343157

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Joon Goo Hong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/82345 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Multi-Vt horizontal nanosheet devices and a method of making the same. In one embodiment, an integrated circuit includes a plurality of horizontal nanosheet devices (hNS devices) on a top surface of a substrate, the plurality of hNS devices including a first hNS device and a second hNS device spaced apart from each other horizontally. Each of the hNS devices includes a first and a second horizontal nanosheets spaced apart vertically; and a gate stack between the first and second horizontal nanosheets, the gate stack including a work function metal (WFM) layer. A thickness of the first and second horizontal nanosheets of the first hNS device is different from a thickness of the first and second horizontal nanosheets of the second hNS device, and a thickness of the WFM layer of the first hNS device is different from a thickness of the WFM layer of the second hNS device.

公开(公告)号：US09853114B1

公开(公告)日：2017-12-26

申请号：US15458655

申请日：2017-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna Obradovic

IPC: H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/161 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78696

Abstract: A field effect transistor (FET) for an nFET and/or a pFET device including a fin having a stack of nanowire-like channel regions. The stack includes at least a first nanowire-like channel region and a second nanowire-like channel region stacked on the first nanowire-like channel region. The FET includes source and drain electrodes on opposite sides of the fin. The FET also includes a dielectric separation region including SiGe between the first and second nanowire-like channel regions extending completely from a surface of the second channel region facing the first channel region to a surface of the first channel region facing the second channel region. The FET includes a gate stack extending along a pair of sidewalls of the stack. The gate stack includes a gate dielectric layer and a metal layer on the gate dielectric layer. The metal layer does not extend between the first and second nanowire-like channel regions.

公开(公告)号：US09773886B1

公开(公告)日：2017-09-26

申请号：US15340827

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167

CPC classification number: H01L29/66553 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

公开(公告)号：US20170271474A1

公开(公告)日：2017-09-21

申请号：US15346535

申请日：2016-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Mark S. Rodder

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/66522 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/66856 ,  H01L29/778 ,  H01L29/7783 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/7853

Abstract: According to an embodiment of the present invention, a method of manufacturing a FET device having a set BTBT leakage and a maximum VDD includes: determining an x value in InxGa1−xAs according to the BTBT leakage and the maximum VDD, and forming a channel utilizing InxGa1−xA, wherein x is not 0.53.

公开(公告)号：US09691860B2

公开(公告)日：2017-06-27

申请号：US14698817

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Rwik Sengupta

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/1054 ,  H01L29/66 ,  H01L29/66795

Abstract: A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

公开(公告)号：US09685509B2

公开(公告)日：2017-06-20

申请号：US14226518

申请日：2014-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Mark S. Rodder ,  Robert C. Bowen

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/086 ,  H01L29/0878 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.