知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

159 条记录 (耗时 0.035 秒)

    Method of Forming Metal Gates and Metal Contacts in a Common Fill Process
    82.
    发明申请
    Method of Forming Metal Gates and Metal Contacts in a Common Fill Process 有权
    在普通填充工艺中形成金属门和金属触点的方法

    公开(公告)号：US20120282765A1

    公开(公告)日：2012-11-08

    申请号：US13100798

    申请日：2011-05-04

    申请人： Ronny Pfützner ,  Ralf Richter ,  Jens Heinrich

    发明人： Ronny Pfützner ,  Ralf Richter ,  Jens Heinrich

    IPC分类号： H01L21/3213

    CPC分类号： H01L21/823871 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828

    摘要： The method described herein involves a method of forming metal gates and metal contacts in a common fill process. The method may involve forming a gate structure comprising a sacrificial gate electrode material, forming at least one conductive contact opening in a layer of insulating material positioned adjacent the gate structure, removing the sacrificial gate electrode material to thereby define a gate electrode opening, and performing a common deposition process to fill the conductive contact opening and the gate electrode opening with a conductive fill material.

    摘要翻译： 本文描述的方法涉及在公共填充过程中形成金属栅极和金属触点的方法。 该方法可以包括形成包括牺牲栅电极材料的栅极结构，在邻近栅结构定位的绝缘材料层中形成至少一个导电接触开口，去除牺牲栅电极材料，从而限定栅电极开口，并执行 用于用导电填充材料填充导电接触开口和栅电极开口的公共沉积工艺。

    Methods for fabricating semiconductor devices having local contacts
    84.
    发明授权
    Methods for fabricating semiconductor devices having local contacts 有权
    制造具有局部接触的半导体器件的方法

    公开(公告)号：US08216928B1

    公开(公告)日：2012-07-10

    申请号：US13014561

    申请日：2011-01-26

    申请人： Ralf Richter ,  Torsten Huisinga ,  Jens Heinrich

    发明人： Ralf Richter ,  Torsten Huisinga ,  Jens Heinrich

    IPC分类号： H01L21/44

    CPC分类号： H01L21/823807 ,  H01L21/76801 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53295 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure that includes a gate structure overlying a semiconductor substrate and a doped region formed in the semiconductor substrate adjacent to the gate structure involves the steps of forming a first layer of dielectric material overlying the gate structure and the doped region, isotropically etching the first layer of dielectric material, forming a second layer of dielectric material overlying the first layer of dielectric material after isotropically etching the first layer, and forming a conductive contact that is electrically connected to the doped region within the first layer and the second layer.

    摘要翻译： 提供半导体器件结构的制造方法。 制造半导体器件结构的一种方法包括覆盖半导体衬底的栅极结构和形成在与栅极结构相邻的半导体衬底中的掺杂区域的半导体器件结构包括以下步骤：形成覆盖栅极结构和掺杂区域的第一绝缘材料层 各向同性蚀刻所述第一介电材料层，在各向同性蚀刻所述第一层之后形成覆盖所述第一介电材料层的第二介电材料层，以及形成电连接到所述第一层内的所述掺杂区域的导电接触，以及 第二层。

    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    85.
    发明授权
    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
    在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法

    公开(公告)号：US08198190B2

    公开(公告)日：2012-06-12

    申请号：US12103765

    申请日：2008-04-16

    申请人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    发明人： Ralf Richter ,  Robert Seidel ,  Juergen Boemmels ,  Thomas Foltyn

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/7681 ,  H01L21/76811 ,  H01L21/76816

    摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译： 中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层 连接在共同的图案化过程中。 此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率 比寄生电容。

    Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric
    87.
    发明申请
    Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric 审中-公开
    基于非保形层间介质的高K金属栅极堆叠的替代栅极方法

    公开(公告)号：US20120001263A1

    公开(公告)日：2012-01-05

    申请号：US12970261

    申请日：2010-12-16

    申请人： Ralf Richter ,  Kai Frohberg

    发明人： Ralf Richter ,  Kai Frohberg

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/76837 ,  H01L21/31053 ,  H01L21/76819 ,  H01L29/7833 ,  Y02P80/30

    摘要： In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal.

    摘要翻译： 在用于在后期制造阶段形成复杂的高k金属栅电极结构的替代栅极方法中，占位符材料的暴露可以基于基本均匀的层间电介质材料来实现，例如以氮化硅材料的形式 ，其可以具有与电介质盖材料相同的去除速率，栅电极结构的间隔元件等。 因此，可以避免层间绝缘材料的显着程度的凹陷，从而降低在去除栅极金属的多余材料时形成金属残留物的风险。

    Increased reliability for a contact structure to connect an active region with a polysilicon line
    88.
    发明授权
    Increased reliability for a contact structure to connect an active region with a polysilicon line 有权
    提高接触结构将有源区域与多晶硅线路连接的可靠性

    公开(公告)号：US07906815B2

    公开(公告)日：2011-03-15

    申请号：US12056362

    申请日：2008-03-27

    申请人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

    发明人： Carsten Peters ,  Ralf Richter ,  Kai Frohberg

    IPC分类号： H01L21/70

    CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria.

    摘要翻译： 通过形成直接接触结构，例如通过在硅化处理之前去除侧壁间隔物，在增加量的金属硅化物的基础上连接有源区域，可以在接触期间实现显着增加的蚀刻选择性 蚀刻停止层开口。 因此，有效区域的高掺杂硅材料的过度蚀刻将被抑制。 附加地或替代地，公开了适当设计的测试结构，其可以检测根据特定制造顺序形成的接触结构的电特性，并且可以基于特定的设计标准。

    CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PROCESS
    90.
    发明申请
    CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PROCESS 有权
    通过使用蚀刻工艺在高K金属栅格叠层中去除CAP层

    公开(公告)号：US20100330808A1

    公开(公告)日：2010-12-30

    申请号：US12824534

    申请日：2010-06-28

    申请人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

    发明人： Ralf Richter ,  Frank Seliger ,  Martin Mazur

    IPC分类号： H01L21/311

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

    摘要： In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

    摘要翻译： 在替代栅极方法中，在单独的去除工艺（例如等离子体辅助蚀刻工艺）中去除栅电极结构的电介质盖层，以便在层间电介质材料随后的平坦化期间提供优异的工艺条件， 牺牲栅材料。 由于优异的工艺条件，牺牲栅极材料的选择性去除可以通过增强的均匀性来实现，从而也有助于晶体管特性的优异的稳定性。